TMS320F28062F datasheet(44/204 Pages) TI2

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8.1.3 Viterbi, Complex Math, CRC Unit (VCU)

The C28x VCU enhances the processing power of C2000™ devices by adding additional assembly instructions

to target complex math, Viterbi decode, and CRC calculations. The VCU instructions accelerate many

applications, including the following:

• Orthogonal frequency-division multiplex (OFDM) used in the PRIME and G3 standards for power line

communications

• Short-range radar complex math calculations

• Power calculations

• Memory and data communication packet checks (CRC)

The VCU features include:

• Instructions to support Cyclic Redundancy Checks (CRCs), which is a polynomial code checksum.

– CRC8

– CRC16

– CRC32

• Instructions to support a flexible software implementation of a Viterbi decoder

– Branch metric calculations for a code rate of 1/2 or 1/3

– Add-Compare Select or Viterbi Butterfly in five cycles per butterfly

– Traceback in three cycles per stage

– Easily supports a constraint length of K = 7 used in PRIME and G3 standards

• Complex math arithmetic unit

– Single-cycle Add or Subtract

– 2-cycle multiply

– 2-cycle multiply and accumulate (MAC)

– Single-cycle repeat MAC

• Independent register space

8.1.4 Memory Bus (Harvard Bus Architecture)

As with many MCU-type devices, multiple buses are used to move data between the memories and peripherals

and the CPU. The memory bus architecture contains a program read bus, data read bus, and data write bus.

The program read bus consists of 22 address lines and 32 data lines. The data read and write buses consist

of 32 address lines and 32 data lines each. The 32-bit-wide data buses enable single cycle 32-bit operations.

The multiple bus architecture, commonly termed Harvard Bus, enables the C28x to fetch an instruction, read a

data value and write a data value in a single cycle. All peripherals and memories attached to the memory bus

prioritize memory accesses. Generally, the priority of memory bus accesses can be summarized as follows:

Highest:

Data Writes

(Simultaneous data and program writes cannot occur on the memory bus.)

Program Writes

(Simultaneous data and program writes cannot occur on the memory bus.)

Data Reads

Program Reads

(Simultaneous program reads and fetches cannot occur on the

memory bus.)

Lowest:

Fetches

(Simultaneous program reads and fetches cannot occur on the

memory bus.)

TMS320F28069, TMS320F28069M, TMS320F28069F, TMS320F28068M, TMS320F28068F

TMS320F28067, TMS320F28066, TMS320F28065, TMS320F28064, TMS320F28063

TMS320F28062, TMS320F28062F

SPRS698J – NOVEMBER 2010 – REVISED SEPTEMBER 2021

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TMS320F28062F Datasheet(PDF) 44 Page - Texas Instruments

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