TMS320F28062F datasheet(13/204 Pages) TI2

13 / 204 page

PIN NAME

PIN NO.

I/O/Z(1)

DESCRIPTION

PZP

PFP

CLOCK

XCLKOUT

See GPIO18

O/Z

See GPIO18. Output clock derived from SYSCLKOUT. XCLKOUT is either the same

frequency, one-half the frequency, or one-fourth the frequency of SYSCLKOUT. This

is controlled by bits 1:0 (XCLKOUTDIV) in the XCLK register. At reset, XCLKOUT =

SYSCLKOUT/4. The XCLKOUT signal can be turned off by setting XCLKOUTDIV to 3.

The mux control for GPIO18 must also be set to XCLKOUT for this signal to propogate

to the pin.

XCLKIN

See GPIO19 and

GPIO38

See GPIO19 and GPIO38. External oscillator input. Pin source for the clock is

controlled by the XCLKINSEL bit in the XCLK register, GPIO38 is the default selection.

This pin feeds a clock from an external 3.3-V oscillator. In this case, the X1 pin, if

available, must be tied to GND and the on-chip crystal oscillator must be disabled

through bit 14 in the CLKCTL register. If a crystal or resonator is used, the XCLKIN

path must be disabled by bit 13 in the CLKCTL register.

NOTE: Designs that use the GPIO38/XCLKIN/TCK pin to supply an external clock

for normal device operation may need to incorporate some hooks to disable this path

during debug using the JTAG connector. This is to prevent contention with the TCK

signal, which is active during JTAG debug sessions. The zero-pin internal oscillators

may be used during this time to clock the device.

On-chip 1.8-V crystal-oscillator input. To use this oscillator, a quartz crystal or a ceramic

resonator must be connected across X1 and X2. In this case, the XCLKIN path must be

disabled by bit 13 in the CLKCTL register. If this pin is not used, it must be tied to GND.

On-chip crystal-oscillator output. A quartz crystal or a ceramic resonator must be

connected across X1 and X2. If X2 is not used, it must be left unconnected.

RESET

XRS

I/OD

Device Reset (in) and Watchdog Reset (out). These devices have a built-in power-

on reset (POR) and brownout reset (BOR) circuitry. During a power-on or brownout

condition, this pin is driven low by the device. An external circuit may also drive this

pin to assert a device reset. This pin is also driven low by the MCU when a watchdog

reset occurs. During watchdog reset, the XRS pin is driven low for the watchdog

reset duration of 512 OSCCLK cycles. A resistor with a value from 2.2 kΩ to 10 kΩ

should be placed between XRS and VDDIO. If a capacitor is placed between XRS

and VSS for noise filtering, it should be 100 nF or smaller. These values will allow

the watchdog to properly drive the XRS pin to VOL within 512 OSCCLK cycles when

the watchdog reset is asserted. Regardless of the source, a device reset causes the

device to terminate execution. The program counter points to the address contained at

the location 0x3F FFC0. When reset is deactivated, execution begins at the location

designated by the program counter. The output buffer of this pin is an open-drain

device with an internal pullup. (↑) If this pin is driven by an external device, it should be

done using an open-drain device.

ADC, COMPARATOR, ANALOG I/O

ADCINA7

–

ADC Group A, Channel 7 input

ADCINA6

ADC Group A, Channel 6 input

COMP3A

Comparator Input 3A

AIO6

I/O

Digital AIO 6

ADCINA5

ADC Group A, Channel 5 input

ADCINA4

ADC Group A, Channel 4 input

COMP2A

Comparator Input 2A

AIO4

I/O

Digital AIO 4

ADCINA3

–

ADC Group A, Channel 3 input

ADCINA2

ADC Group A, Channel 2 input

COMP1A

Comparator Input 1A

AIO2

I/O

Digital AIO 2

ADCINA1

ADC Group A, Channel 1 input

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TMS320F28069, TMS320F28069M, TMS320F28069F, TMS320F28068M, TMS320F28068F

TMS320F28067, TMS320F28066, TMS320F28065, TMS320F28064, TMS320F28063

TMS320F28062, TMS320F28062F

SPRS698J – NOVEMBER 2010 – REVISED SEPTEMBER 2021

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TMS320F28062 TMS320F28062F

TMS320F28062F Datasheet(PDF) 13 Page - Texas Instruments

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