Data Sheet

ADPL21504

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Rev. 0

9 of 16

THEORY OF OPERATION

The ADPL21504 uses a constant off-time control scheme to provide high efficiencies over a wide range of output

currents. Figure 4 (Block Diagram) provides the best understanding of the operation. Q1 and Q2, along with R3 and

R4, form a bandgap reference used to regulate the output voltage. When the voltage at the FB pin is slightly above

1.23V, comparator A1 disables most of the internal circuitry. The Output current is then provided by capacitor C2,

which slowly discharges until the voltage at the FB pin drops below the lower hysteresis point of A1 (typical hysteresis

at the FB pin is 8mV).

A1 then enables the internal circuitry, turns on power switch Q3, and the current in inductor L1 begins ramping up.

Once the switch current reaches 350mA, comparator A2 resets the one shot, which turns off Q3 for 400ns. L1 then

delivers current to the output through diode D1 as the inductor current ramps down. Q3 turns on again, and the

inductor current ramps back up to 350mA, then A2 resets the one shot, again allowing L1 to deliver current to the

output. This switching action continues until the output voltage is charged up (until the FB pin reaches 1.23V), and

then A1 turns off the internal circuitry, and the cycle repeats. The ADPL21504 contains additional circuitry to provide

protection during start-up and under short-circuit conditions. When the FB pin voltage is less than approximately

600mV, the switch off-time is increased to 1.5µs, and the current limit is reduced to around 250mA (70% of its normal

value). This reduces the average inductor current and helps minimize the power dissipation in the ADPL21504 power

switch and in the external inductor and diode.