7.2.1 Design Requirements

Table 7-1 lists the parameters for this typical application.

Table 7-1. Design Requirements

PARAMETER

VALUE

System voltage, power-stage

48V

Bootstrap supply voltage (VBS)

6V

Maximum ripple voltage on AVDD supply (VRIPPLE)

200mV

PWM frequency

16kHz

PWM duty cycle range

5% to 95%

Linear current sensing range

±5A

7.2.2 Detailed Design Procedure

In Figure 7-1, the high-side power supply (AVDD) is generated from a bootstrap circuit (R4, D1, C2).

The high-side ground reference (GND1) is derived from the end of the shunt resistor connected to the negative

input of the AMC0100R (INN). For a four-terminal shunt, connect the device inputs to the inner leads of the shunt

and connect GND1 to the outer leads. To minimize offset and improve accuracy, route the ground connection as

a separate trace. Connect GND1 directly to the shunt resistor rather than shorting GND1 to INN at the input to

the device. See the Layout section for more details.

7.2.2.1 Shunt Resistor Sizing

The shunt resistor (RSHUNT) value is determined by the device linear input voltage range (±250mV) and the

desired linear current sensing range of ±5A. RSHUNT is calculated as 250mV / 5A = 50mΩ. The peak power

dissipated in the shunt resistor is RSHUNT × IPEAK 2 = 50mΩ × (5A)2 = 1.25W. For a linear response, operate

the shunt resistor at no more than 2/3 of the rated power. Therefore, a shunt resistor with a nominal power rating

of approximately 1.8W is selected.

Select a lower shunt resistor value if transient overcurrents are expected in the system that exceed the linear

input voltage range of the AMC0100R. However, if reduced linearity and lower resolution is acceptable for

the overcurrent range, allow the voltage drop across the shunt to exceed the linear input voltage range up

to the clipping voltage of the AMC0100R. In any case, make sure the voltage drop caused by the maximum

overcurrent does not exceed the input voltage that causes a clipping output. That is, make sure |VSHUNT| ≤

|VClipping|.

7.2.2.2 Input Filter Design

Place a differential RC filter (R1, R2, C5) in front of the isolated amplifier to improve signal-to-noise performance

of the signal path. Design the input filter such that:

• The cutoff frequency of the filter is at least one order of magnitude lower than the sampling frequency

(20MHz) of the ΔΣ modulator

• The input bias current does not generate significant voltage drop across the DC impedance of the input filter

• The impedances measured from the analog inputs are equal

Place capacitors C6 and C7 to improve common-mode rejection at high frequencies (>1MHz) and to improve

offset voltage performance. For best performance, verify C6 matches the value of C7 and that both capacitors

are 10 to 20 times lower in value than C5. NP0-type capacitors offer low temperature drift and low voltage

coefficients, and are preferred for common-mode filtering.

For most applications, the structure shown in Figure 7-2 achieves excellent performance.

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AMC0100R

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