TPS56520PWPR datasheet(22/51 Pages) TI2

22 / 51 page

TPS56C20, TPS56920, TPS56720, TPS56520

SLVSCB6E – NOVEMBER 2013 – REVISED DECEMBER 2017

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Product Folder Links: TPS56C20 TPS56920 TPS56720 TPS56520

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8.6.4 Control Registers

There are 4 control registers: Registers 0, 8, 9 and 24.

Table 3. Summary of Default Control Bits

CONTROL BIT(s)

DEFAULT

(BINARY)

FUNCTION

VOUT[7:0]

0110010

VOUT code, 7 bits VOUT[6:0] + odd parity checksum bit at VOUT[7]

Writing a valid code to this register also sets Internal Mode.

Sending an invalid code (checksum incorrect) to this register does not change register contents

or set Internal/Enable bits.

Internal Mode

(EXTERNAL

mode)

1. If set to 1, the part switches to INTERNAL mode and VOUT register value controls output

voltage.

2. Writing a valid code to the VOUT register sets this Internal Mode bit to 1.

3. The part can be set back to EXTERNAL control mode at any time by writing this bit to 0.

PGOOD Delay [1:0]

Part defaults to PGOOD Delay = 26.4µS

Hiccup Mode

Part defaults to Hiccup Mode On. If Hiccup Mode is enabled, do not turn on OVP Latchoff

Mode and/or UVP Latchoff Mode.

ECO Mode

Part defaults to ECO Mode Off

DAC Settle [1:0]

Part defaults to DAC Settle = 25µS

Enable

Part defaults to Disabled.

This bit can be set to 1 by writing the bit to 1. The external EN terminal being set to 1 overrides

the register value (you cannot disable the part by writing a 0 if the EN terminal is high).

OVP Latchoff Mode

Disable

Part defaults to Latchoff Mode Off. If Hiccup Mode is enabled, do not turn on OVP Latchoff

Mode and/or UVP Latchoff Mode.

UVP Latchoff Mode

Disable

Part defaults to Latchoff Mode Off. If Hiccup Mode is enabled, do not turn on OVP Latchoff

Mode and/or UVP Latchoff Mode.

CurLim[2:0]

111

Selects default current limit value

Enable: This bit can be used to enable the regulator just like setting the EN terminal high. The EN terminal has

priority (if EN=high, the Enable bit does nothing, the chip is already enabled). This allows the customer to tie EN

to GND externally or leave the EN terminal floating (the terminal is pulled low internally) and subsequently enable

the regulator by I2C software control.

DAC Settle [1:0]: When a new VOUT voltage is selected, this happens by setting an internal DAC to a new

internal VREF voltage. If this happens instantly, the regulator loop will be thrown out of regulation and the

DCAP2 loop must respond to bring the VOUT back into regulation at its new chosen value. This can cause

VOUT overshoots (or undershoots) or head to high transient input currents. Therefore, an analog filter on the

DAC output causes this internal VREF to change more slowly. The DAC Settle[1:0] bits change the filter time

constant as follows:

DAC Settle [1:0]

Typical Filter Time Constant

6 µs

10 µs

15 µs

25 µs

The power-up default value of the DAC Settle[1:0] bits is 11.

Internal Mode: This bit can be interrogated to discover whether the chip is running in EXT Mode (using external

resistor dividers to VFB terminal to set the output voltage) or INT Mode (using codes set in Output Voltage

Writing a valid value to a VOUT register always sets External to 1 on the corresponding regulator.

In default, the TPS56X20 will start up into external mode and the output voltage is set by VFB with divider

resistors. If starting up into internal VID mode is desired, the input voltage should be applied first, write Internal

Mode bit to "1" the next, then enable the device by EN terminal or EN bit.

TPS56520PWPR Datasheet(PDF) 22 Page - Texas Instruments

TPS56520PWPR Datasheet(HTML) 22 Page - Texas Instruments

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