capacitor must be 100pF. For voltages greater than 1.8V, calculate the approximate value of this capacitor as

given in the Functional Block Diagrams.

7.2.3 Application Curves

Time (

s)

0

80

160

240

320

400

480

560

0

-80

20

-70

40

-60

60

-50

80

-40

100

-30

120

-20

140

-10

160

0

180

10

200

20

220

30

240

40

260

50

IOUT

VOUT

Figure 7-5. TPS792xx Load Transient Response

Time (

s)

0

50

100 150 200 250 300 350 400 450 500 550

3.6

-25

4

-20

4.4

-15

4.8

-10

5.2

-5

5.6

0

6

5

6.4

10

6.8

15

7.2

20

7.6

25

8

30

VIN

VOUT

Figure 7-6. TPS792xx Line Transient Response

7.3 Power Supply Recommendations

This device is designed to operate from an input voltage supply range from 2.7V to 5.5V. The input voltage

range must provide adequate headroom for the device to have a regulated output. This input supply must be

well-regulated and stable. A 0.1µF input capacitor is required for stability (legacy chip) or a 1µF (new chip); if the

input supply is noisy, additional input capacitors with low ESR can help improve the output noise performance.

7.4 Layout

7.4.1 Layout Guidelines

Layout is a critical part of good power-supply design. There are several signal paths that conduct fast-changing

currents or voltages that can interact with stray inductance or parasitic capacitance to generate noise or degrade

the power-supply performance. To help eliminate these problems, the IN pin should be bypassed to ground with

a low ESR ceramic bypass capacitor with an X5R or X7R dielectric.

Equivalent series inductance (ESL) and equivalent series resistance (ESR) must be minimized to maximize

performance and ensure stability. Every capacitor (CIN, COUT, CNR, CFF) must be placed as close as possible

to the device and on the same side of the PCB as the regulator itself. Do not place any of the capacitors on

the opposite side of the PCB from where the regulator is installed. The use of vias and long traces is strongly

discouraged because these circuits may impact system performance negatively, and even cause instability.

7.4.1.1 Board Layout Recommendations to Improve PSRR and Noise Performance

To improve ac measurements like PSRR, output noise, and transient response, it is recommended that the board

be designed with separate ground planes for VIN and VOUT, with each ground plane connected only at the GND

pin of the device. In addition, the ground connection for the bypass capacitor should connect directly to the GND

pin of the device.

7.4.1.2 Power Dissipation and Junction Temperature

Specified regulator operation is to a junction temperature of 125°C; the maximum junction temperature should

be restricted to 125°C under normal operating conditions. This restriction limits the power dissipation the

regulator can handle in any given application. To ensure the junction temperature is within acceptable limits,

calculate the maximum allowable dissipation, PD(max), and the actual dissipation, PD, which must be less than or

equal to PD(max).

The maximum power dissipation limit is determined using Equation 4.

TPS792

SLVS337E – MARCH 2001 – REVISED JANUARY 2025

www.ti.com

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