TUSB1064I datasheet(28/50 Pages) TI2

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TUSB1064

SLLSF48C – MARCH 2018 – REVISED SEPTEMBER 2019

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Table 16. USB3.1 Control/Status Registers (0x20)

Bit

Field

Type

Reset

Description

7:4

EQ2_SEL

R/W/U

0000

Field selects EQ level for USB3.1 RX2 receiver. When

EQ_OVERRIDE = 1’b0, this field reflects the sampled state of

EQ[1:0] pins. When EQ_OVERRIDE = 1’b1, software can

change the EQ setting for USB3.1 RX2 receiver based on value

written to this field.

3:0

EQ1_SEL

R/W/U

0000

Field selects EQ level for USB3.1 RX1 receiver. When

EQ_OVERRIDE = 1’b0, this field reflects the sampled state of

EQ[1:0] pins. When EQ_OVERRIDE = 1’b1, software can

change the EQ setting for USB3.1 RX1 receiver based on value

written to this field.

8.6.7 USB3.1 Control/Status Registers (address = 0x21) [reset = 00000000]

Figure 24. USB3.1 Control/Status Registers (0x21)

Reserved

SSEQ_SEL

R/W/U

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 17. USB3.1 Control/Status Registers (0x21)

Bit

Field

Type

Reset

Description

7:4

Reserved

0000

Reserved

3:0

SSEQ_SEL

R/W/U

0000

Field selects EQ for USB3.1 SSTXP/N receiver. When

EQ_OVERRIDE = 1’b0, this field reflects the sampled state of

SSEQ[1:0] pins. When EQ_OVERRIDE = 1’b1, software can

change the EQ setting for USB3.1 SSTXP/N receiver based on

value written to this field.

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