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DM505 Datasheet(PDF) 154 Page - Texas Instruments

Part # DM505
Description  DM505 SoC for Vision Analytics 15mm Package (ABF) Silicon Revision 2.0
PDF  295 Pages
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Manufacturer  TI2 [Texas Instruments]
Direct Link  https://www.ti.com
Logo TI2 - Texas Instruments

DM505 Datasheet(HTML) 154 Page - Texas Instruments

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154
DM505
SPRS976E – NOVEMBER 2016 – REVISED MAY 2018
www.ti.com
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Specifications
Copyright © 2016–2018, Texas Instruments Incorporated
Table 5-48. McSPI1/3 IOSETs (continued)
SIGNALS
IOSET1
IOSET2
IOSET3
BALL
MUX
BALL
MUX
BALL
MUX
spi1_d0
T5
0
T5
0
T5
0
spi1_cs0
R6
0
R6
0
R6
0
spi1_cs1
R5
0
spi1_cs2
F14
5
spi1_cs3
C14
5
SPI3
spi3_sclk
F15
4
C6
4
spi3_d1
D14
4
F7
4
spi3_d0
D15
4
E7
4
spi3_cs0
F16
4
B6
4
5.9.6.11 QSPI
The Quad SPI (QSPI) module is a type of SPI module that allows single, dual or quad read access to
external SPI devices. This module has a memory mapped register interface, which provides a direct
interface for accessing data from external SPI devices and thus simplifying software requirements. It
works as a master only. There is one QSPI module in the device and it is primary intended for fast
booting from quad-SPI flash memories.
General SPI features:
•
Programmable clock divider
•
Six pin interface (DCLK, CS_N, DOUT, DIN, QDIN1, QDIN2)
•
4 external chip select signals
•
Support for 3-, 4- or 6-pin SPI interface
•
Programmable CS_N to DOUT delay from 0 to 3 DCLKs
•
Programmable signal polarities
•
Programmable active clock edge
•
Software controllable interface allowing for any type of SPI transfer
NOTE
For more information, see the Quad Serial Peripheral Interface section of the Device TRM.
CAUTION
The IO Timings provided in this section are only valid when all QSPI Chip
Selects used in a system are configured to use the same Clock Mode (either
Clock Mode 0 or Clock Mode 3).
Table 5-49 and Table 5-50 present Timing and Switching Characteristics for Quad SPI Interface.



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