DM505 datasheet(215/295 Pages) TI2

215 / 295 page

BGA pad on PCB

Source Component

Load Component

Static IR drop and Effective Resistance

PCB

SPRS977_PCB_STATIC_02

215

DM505

www.ti.com

SPRS976E – NOVEMBER 2016 – REVISED MAY 2018

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Applications, Implementation, and Layout

Figure 7-4. Static IR Drop Budget for PCB Only

The system-level IR drop budget is made up of three portions: on-chip, package, and PCB board. Static IR

or dc analysis/design methodology consists of designing the PDN such that the voltage drop (under dc

operating conditions) across power and ground pads of the transistors of the application processor device

is within a specified value of the nominal voltage for proper functionality of the device.

A PCB system-level voltage drop budget for proper device functionality is typically 1.5% of nominal

voltage. For a 1.35-V supply, this would be

≤20 mV.

To accurately analyze PCB static IR drop, the actual geometry of the PDN must be modeled properly and

simulated to accurately characterize long distribution paths, copper weight impacts, electro-migration

violations of current-carrying vias, and "Swiss-cheese” effects via placement has on power rails. It is

recommended to perform the following analyses:

•

Lumped resistance/IR drop analysis

•

Distributed resistance/IR drop analysis

NOTE

The PMIC companion device supporting Processor has been designed with voltage sensing

feedback loop capabilities that enable a remote sense of the SMPS output voltage at the

point of use.

The NOTE above means the SMPS feedback signals and returns must be routed across PCB and

connected to the Device input power ball for which a particular SMPS is supplying power. This feedback

loop provides compensation for some of the voltage drop encountered across the PDN within limits. As

such, the effective resistance of the PDN within this loop should be determined in order to optimize

voltage compensation loop performance. The resistance of two PDN segments are of interest: one from

the power inductor/bulk power filtering capacitor node to the Processor’s input power and second is the

entire PDN route from SMPS output pin/ball to the Processor input power.

In the following sections each methodology is described in detail and an example has been provided of

analysis flow that can be used by the PCB designer to validate compliance to the requirements on their

PCB PDN design.

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