DM505 datasheet(106/295 Pages) TI2

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DEVICE

clkout0

To quartz (from oscillator output).

resetn

rstoutn

External Reference Clock [0:2].

For Audio and other Peripherals

xref_clk1

sysboot[15:0]

From quartz (19.2, 20 or 27 MHz)

or from CMOS square clock source (19.2, 20 or 27MHz).

Boot Mode Configuration

xi_osc1

Warm reset output.

Device reset input.

porz

Power ON Reset.

xi_osc0

xo_osc0

xo_osc1

From quartz (range from

MHz)

or from CMOS square clock source(range from

MHz).

19.2 to 32

12 to 38.4

To quartz (from oscillator output).

clkout1

clkout2

xref_clk0

Output clkout[0:2] clocks come from:

• Either the input system clock and alternate clock (xi_osc0 or xi_osc1)

• Or a CORE clock (from CORE output)

• Or a 192-MHz clock (from PER DPLL output).

SPRS91v_CLK_01_SR2.0

xref_clk2

106

DM505

SPRS976E – NOVEMBER 2016 – REVISED MAY 2018

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Specifications

–

can start to ramp down before or concurrently with vdds18v.

–

must not exceed vdds18v voltage level after vdds18v drops below 1.62 V until vdds18v drops below VOFF (0.6 V).

(10) vdds18v domain should maintain a minimum level of 1.62 V (VNOM – 10%) until vdd_dspeve and vdd start to ramp down.

5.9.4

Clock Specifications

NOTE

For more information, see Power, Reset, and Clock Management / PRCM Subsystem

Environment / External Clock Signals and Clock Management Functional Description section

of the Device TRM.

NOTE

Audio Back End (ABE) module is not supported for this family of devices, but “ABE” name is

still present in some clock or DPLL names.

The device operation requires the following clocks:

•

The system clocks, SYS_CLK1(Mandatory) and SYS_CLK2(Optional) are the main clock sources of

the device. They supply the reference clock to the DPLLs as well as functional clock to several

modules.

Figure 5-10 shows the external input clock sources and the output clocks to peripherals.

Figure 5-10. Clock Interface

DM505 Datasheet(PDF) 106 Page - Texas Instruments

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