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DM505LRBABF Datasheet(PDF) 138 Page - Texas Instruments

Part # DM505LRBABF
Description  DM505 SoC for Vision Analytics 15mm Package (ABF) Silicon Revision 2.0
PDF  295 Pages
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Manufacturer  TI2 [Texas Instruments]
Direct Link  https://www.ti.com
Logo TI2 - Texas Instruments

DM505LRBABF Datasheet(HTML) 138 Page - Texas Instruments

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GPMC_FCLK
gpmc_clk
gpmc_csi
gpmc_a27
gpmc_ben0
gpmc_
1
ben
gpmc_
_ale
advn
gpmc_oen_ren
gpmc_a [15:0]
d
DIR
gpmc_waitj
Address (MSB)
Valid
Valid
Address (LSB)
Data IN
Data IN
OUT
OUT
IN
OUT
FA0
FA9
FA10
FA3
FA13
FA29
FA1
FA37
FA12
FA4
FA10
FA0
FA5
FA14
FA15
GPMC_11
gpmc_a[10:1]
138
DM505
SPRS976E – NOVEMBER 2016 – REVISED MAY 2018
www.ti.com
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Specifications
Copyright © 2016–2018, Texas Instruments Incorporated
Figure 5-32. GPMC / Multiplexed NOR Flash - Asynchronous Read - Single Word Timing(1)(2)(3)
(1) In “gpmc_csi”, i = 0 to 7. In “gpmc_waitj”, j = 0 to 1
(2) FA5 parameter illustrates amount of time required to internally sample input Data. It is expressed in number of GPMC functional clock
cycles. From start of read cycle and after FA5 functional clock cycles, input Data will be internally sampled by active functional clock
edge. FA5 value should be stored inside AccessTime register bits field.
(3) GPMC_FCLK is an internal clock (GPMC functional clock) not provided externally
(4) The "DIR" (direction control) output signal is NOT pinned out on any of the device pads. It is an internal signal only representing a signal
direction on the GPMC data bus.



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