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DM505LRBABF Datasheet(PDF) 135 Page - Texas Instruments

Part # DM505LRBABF
Description  DM505 SoC for Vision Analytics 15mm Package (ABF) Silicon Revision 2.0
PDF  295 Pages
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Manufacturer  TI2 [Texas Instruments]
Direct Link  https://www.ti.com
Logo TI2 - Texas Instruments

DM505LRBABF Datasheet(HTML) 135 Page - Texas Instruments

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GPMC_FCLK
gpmc_clk
gpmc_csi
gpmc_a[
:1]
27
gpmc_ben0
gpmc_be 1
n
gpmc_
_ale
advn
gpmc_oen_ren
gpmc_ d[15:0]
a
gpmc_waitj
DIR
Address 0
Address 1
Valid
Valid
Valid
Valid
Data Upper
OUT
OUT
IN
OUT
IN
FA9
FA10
FA3
FA9
FA3
FA13
FA13
FA1
FA1
FA4
FA4
FA12
FA12
FA10
FA0
FA0
FA16
FA0
FA0
FA10
FA10
FA5
FA5
FA14
FA15
FA14
FA15
GPMC_08
135
DM505
www.ti.com
SPRS976E – NOVEMBER 2016 – REVISED MAY 2018
Submit Documentation Feedback
Specifications
Copyright © 2016–2018, Texas Instruments Incorporated
Figure 5-29. GPMC / NOR Flash - Asynchronous Read - 32-bit Timing(1)(2)(3)
(1) In “gpmc_csi”, i = 0 to 7. In “gpmc_waitj”, j = 0 to 1.
(2) FA5 parameter illustrates amount of time required to internally sample input Data. It is expressed in number of GPMC functional clock
cycles. From start of read cycle and after FA5 functional clock cycles, input Data will be internally sampled by active functional clock
edge. FA5 value should be stored inside AccessTime register bits field
(3) GPMC_FCLK is an internal clock (GPMC functional clock) not provided externally
(4) The "DIR" (direction control) output signal is NOT pinned out on any of the device pads. It is an internal signal only representing a signal
direction on the GPMC data bus.



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