DM505LRBABF datasheet(132/295 Pages) TI2

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gpmc_clk

gpmc_csi

gpmc_a[2 :1]

gpmc_

ben

gpmc_ben0

gpmc_

_ale

advn

gpmc_wen

gpmc_ad[15:0]

gpmc_waitj

Address

D 0

D 1

D 2

D 3

F15

F17

F18

F20

F14

F22

F21

GPMC_06

gpio6_16.clkout0

F23

132

DM505

SPRS976E – NOVEMBER 2016 – REVISED MAY 2018

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Specifications

Figure 5-27. GPMC / Non-Multiplexed 16bits NOR Flash - Synchronous Burst Write 4x16bits -

(GpmcFCLKDivider = 0)(1)(2)

(1) In “gpmc_csi”, i = 1 to 7.

(2) In “gpmc_waitj”, j = 0 to 1.

5.9.6.6.2 GPMC/NOR Flash Interface Asynchronous Timing

Table 5-37 and Table 5-38 assume testing over the recommended operating conditions and electrical

characteristic conditions below (see Figure 5-28, Figure 5-29, Figure 5-30, Figure 5-31, Figure 5-32 and

Figure 5-33).

Table 5-37. GPMC/NOR Flash Interface Timing Requirements - Asynchronous Mode

NO.

PARAMETER

DESCRIPTION

MIN

MAX

UNIT

FA5

tacc(DAT)

Data Maximum Access Time (GPMC_FCLK cycles)

H (1)

cycles

FA20

tacc1-pgmode(DAT)

Page Mode Successive Data Maximum Access Time (GPMC_FCLK

cycles)

P (2)

cycles

FA21

tacc2-pgmode(DAT)

Page Mode First Data Maximum Access Time (GPMC_FCLK cycles)

H (1)

cycles

tsu(DV-OEH)

Setup time, read gpmc_ad[15:0] valid before gpmc_oen_ren high

1.9

th(OEH-DV)

Hold time, read gpmc_ad[15:0] valid after gpmc_oen_ren high

DM505LRBABF Datasheet(PDF) 132 Page - Texas Instruments

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