DM505LRBABF datasheet(136/295 Pages) TI2

136 / 295 page

GPMC_FCLK

gpmc_clk

gpmc_csi

gpmc_a[

:1]

gpmc_ben0

gpmc_be 1

gpmc_

_ale

advn

gpmc_oen_ren

gpmc_ d[15:0]

gpmc_waitj

DIR

Add0

Add1

Add2

Add3

Add4

OUT

FA1

FA0

FA18

FA13

FA12

FA0

FA9

FA10

FA21

FA20

FA14

FA15

SPRS91v_GPMC_09

136

DM505

SPRS976E – NOVEMBER 2016 – REVISED MAY 2018

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Specifications

Figure 5-30. GPMC / NOR Flash - Asynchronous Read - Page Mode 4x16-bit Timing(1)(2)(3)(4)

(1) In “gpmc_csi”, i = 0 to 7. In “gpmc_waitj”, j = 0 to 1

(2) FA21 parameter illustrates amount of time required to internally sample first input Page Data. It is expressed in number of GPMC

functional clock cycles. From start of read cycle and after FA21 functional clock cycles, First input Page Data will be internally sampled

by active functional clock edge. FA21 calculation is detailled in a separated application note (ref …) and should be stored inside

AccessTime register bits field.

(3) FA20 parameter illustrates amount of time required to internally sample successive input Page Data. It is expressed in number of GPMC

functional clock cycles. After each access to input Page Data, next input Page Data will be internally sampled by active functional clock

edge after FA20 functional clock cycles. FA20 is also the duration of address phases for successive input Page Data (excluding first

input Page Data). FA20 value should be stored in PageBurstAccessTime register bits field.

(4) GPMC_FCLK is an internal clock (GPMC functional clock) not provided externally

(5) The "DIR" (direction control) output signal is NOT pinned out on any of the device pads. It is an internal signal only representing a signal

direction on the GPMC data bus.

DM505LRBABF Datasheet(PDF) 136 Page - Texas Instruments

DM505LRBABF Datasheet(HTML) 136 Page - Texas Instruments

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