8 Application and Implementation

Note

Information in the following applications sections is not part of the TI component specification, and

TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining

suitability of components for their purposes. Customers should validate and test their design

implementation to confirm system functionality.

8.1 Application Information

8.1.1 I2C Bus Overview

The inter-integrated circuit (I2C) bus is a single-ended, multi-controller, 2-wire bus for efficient inter-IC

communication in half-duplex mode.

I2C uses open-drain technology, requiring two lines, serial data (SDA) and serial clock (SCL), to be connected

to VDD by resistors (see Figure 8-1). Pulling the line to ground is considered a logic zero while letting the line

float is a logic one. This logic is used as a channel access method. Transitions of logic states must occur while

the SCL pin is low. Transitions while the SCL pin is high indicate START and STOP conditions. Typical supply

voltages are 3.3 V and 5 V, although systems with higher or lower voltages are allowed.

SDA

SCL

VDD

RPU

RPU

RPU

RPU

RPU

RPU

RPU

RPU

C

Controller

C

Target

GND

GND

GND

SDA

SCL

GND

SDA

SCL

SDA

SCL

SDA

SCL

DAC

Target

ADC

Target

Figure 8-1. I2C Bus

I2C communication uses a 7-bit address space with 16 reserved addresses, so a theoretical maximum of 112

nodes can communicate on the same bus. In praxis, however, the number of nodes is limited by the specified,

total bus capacitance of 400 pF, which restricts communication distances to a few meters.

The specified signaling rates for the ISO1540-Q1 and ISO1541-Q1 devices are 100 kbps (standard mode), 400

kbps (fast mode), 1 Mbps (fast mode plus).

The bus has two roles for nodes: controller and target. A controller node issues the clock and target addresses,

and also initiates and ends data transactions. A target node receives the clock and addresses and responds to

requests from the controller. Figure 8-2 shows a typical data transfer between controller and target.

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ISO1540-Q1, ISO1541-Q1

SLLSEX0D – NOVEMBER 2016 – REVISED DECEMBER 2022

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Product Folder Links: ISO1540-Q1 ISO1541-Q1