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TDA2SA Datasheet(PDF) 160 Page - Texas Instruments

Part # TDA2SA
Description  TDA2x ADAS Applications Processor 23mm Package (ABC Package) Silicon Revision 2.0
PDF  427 Pages
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Manufacturer  TI2 [Texas Instruments]
Direct Link  https://www.ti.com
Logo TI2 - Texas Instruments

TDA2SA Datasheet(HTML) 160 Page - Texas Instruments

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TDA2SX, TDA2SG, TDA2SA
TDA2HG, TDA2HV, TDA2HF, TDA2LF
SPRS951F – DECEMBER 2015 – REVISED MAY 2019
www.ti.com
Submit Documentation Feedback
Product Folder Links: TDA2SX TDA2SG TDA2SA TDA2HG TDA2HV TDA2HF TDA2LF
Specifications
Copyright © 2015–2019, Texas Instruments Incorporated
Table 5-10. LVCMOS DDR DC Electrical Characteristics (continued)
PARAMETER
MIN
NOM
MAX
UNIT
CPAD
Pad capacitance (including package capacitance)
3
pF
(1) VDDS stands for corresponding power supply (that is vdds_ddr1 or vdds_ddr2). For more information on the power supply name and
the corresponding ball, see Table 4-2, POWER [11] column.
(2) VREF in this table stands for corresponding Reference Power Supply (that is ddr1_vref0 or ddr2_vref0). For more information on the
power supply name and the corresponding ball, see Table 4-2, POWER [11] column.
5.7.2
HDMIPHY DC Electrical Characteristics
The HDMIPHY DC Electrical Characteristics are compliant with the HDMI 1.4a specification and are not
reproduced here.
5.7.3
Dual Voltage LVCMOS I
2C DC Electrical Characteristics
Table 5-11 summarizes the DC electrical characteristics for Dual Voltage LVCMOS I2C Buffers.
NOTE
For more information on the I/O cell configurations, see the Control Module section of the
Device TRM.
Table 5-11. Dual Voltage LVCMOS I2C DC Electrical Characteristics
PARAMETER
MIN
NOM
MAX
UNIT
Signal Names in MUXMODE 0: i2c2_scl; i2c1_scl; i2c1_sda; i2c2_sda;
Balls: F17 / C20 / C21 / C25
I2C Standard Mode – 1.8 V
VIH
Input high-level threshold
0.7*VDDS
V
VIL
Input low-level threshold
0.3*VDDS
V
Vhys
Hysteresis
0.1*VDDS
V
IIN
Input current at each I/O pin with an input voltage
between 0.1*VDDS to 0.9*VDDS
12
µA
IOZ
IOZ(IPAD Current) for BIDI cell. This current is
contributed by the tristated driver leakage + input
current of the Rx + weak pullup/pulldown leakage.
PAD is swept from 0 to VDDS and the Max(I(PAD))
is measured and is reported as IOZ
12
µA
CIN
Input capacitance
10
pF
VOL3
Output low-level threshold open-drain at 3-mA
sink current
0.2*VDDS
V
IOLmin
Low-level output current @VOL=0.2*VDDS
3
mA
tOF
Output fall time from VIHmin to VILmax with a bus
capacitance CB from 5 pF to 400 pF
250
ns
I2C Fast Mode – 1.8 V
VIH
Input high-level threshold
0.7*VDDS
V
VIL
Input low-level threshold
0.3*VDDS
V
Vhys
Hysteresis
0.1*VDDS
V
IIN
Input current at each I/O pin with an input voltage
between 0.1*VDDS to 0.9*VDDS
12
µA
IOZ
IOZ(IPAD Current) for BIDI cell. This current is
contributed by the tristated driver leakage + input
current of the Rx + weak pullup/pulldown leakage.
PAD is swept from 0 to VDDS and the Max(I(PAD))
is measured and is reported as IOZ
12
µA
CIN
Input capacitance
10
pF



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