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TDA2SA Datasheet(PDF) 217 Page - Texas Instruments

Part # TDA2SA
Description  TDA2x ADAS Applications Processor 23mm Package (ABC Package) Silicon Revision 2.0
PDF  427 Pages
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Manufacturer  TI2 [Texas Instruments]
Direct Link  https://www.ti.com
Logo TI2 - Texas Instruments

TDA2SA Datasheet(HTML) 217 Page - Texas Instruments

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vouti_clk
vouti_vsync
vouti_hsync
vouti_d[23:0]
vouti_de
vouti_fld
data_1 data_2
data_n
odd
even
D1
D2
D3
D6
D6
D5
D6
D6
SWPS049-018
D4
vouti_clk
Falling-edge Clock Reference
Rising-edge Clock Reference
217
TDA2SX, TDA2SG, TDA2SA
TDA2HG, TDA2HV, TDA2HF, TDA2LF
www.ti.com
SPRS951F – DECEMBER 2015 – REVISED MAY 2019
Submit Documentation Feedback
Product Folder Links: TDA2SX TDA2SG TDA2SA TDA2HG TDA2HV TDA2HF TDA2LF
Timing Requirements and Switching Characteristics
Copyright © 2015–2019, Texas Instruments Incorporated
(1) P = output vouti_clk period in ns.
(2) SERDES transceivers may be sensitive to the jitter profile of vouti_clk. See Application Note SPRAC62 for additional guidance.
Figure 7-6. DPI Video Output(1)(2)(3)
(1) The configuration of assertion of the data can be programmed on the falling or rising edge of the pixel clock.
(2) The polarity and the pulse width of vouti_hsync and vouti_vsync are programmable, refer to the DSS section of the device TRM.
(3) The vouti_clk frequency can be configured, refer to the DSS section of the device TRM.
NOTE
To configure the desired virtual mode the user must set MODESELECT bit and
DELAYMODE bitfield for each corresponding pad control register.
The pad control registers are presentsed Table 4-3 and described in Device TRM, Control
Module Chapter.
In Table 7-19 are presented the specific groupings of signals (IOSET) for use with VOUT2.
Table 7-19. VOUT2 IOSETs
SIGNALS
IOSET1
IOSET2
BALL
MUX
BALL
MUX
vout2_d23
F2
4
AA4
6
vout2_d22
F3
4
AB3
6
vout2_d21
D1
4
AB9
6
vout2_d20
E2
4
AA3
6
vout2_d19
D2
4
D17
6
vout2_d18
F4
4
G16
6
vout2_d17
C1
4
A21
6
vout2_d16
E4
4
C18
6
vout2_d15
F5
4
A17
6



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