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TDA2SA Datasheet(PDF) 214 Page - Texas Instruments

Part # TDA2SA
Description  TDA2x ADAS Applications Processor 23mm Package (ABC Package) Silicon Revision 2.0
PDF  427 Pages
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Manufacturer  TI2 [Texas Instruments]
Direct Link  https://www.ti.com
Logo TI2 - Texas Instruments

TDA2SA Datasheet(HTML) 214 Page - Texas Instruments

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TDA2SX, TDA2SG, TDA2SA
TDA2HG, TDA2HV, TDA2HF, TDA2LF
SPRS951F – DECEMBER 2015 – REVISED MAY 2019
www.ti.com
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Product Folder Links: TDA2SX TDA2SG TDA2SA TDA2HG TDA2HV TDA2HF TDA2LF
Timing Requirements and Switching Characteristics
Copyright © 2015–2019, Texas Instruments Incorporated
Table 7-14. Manual Functions Mapping for VIP3 (continued)
BALL
BALL NAME
VIP3_MANUAL1
VIP3_MANUAL2
CFG REGISTER
MUXMODE
A_DELAY
(ps)
G_DELAY
(ps)
A_DELAY
(ps)
G_DELAY
(ps)
7
9
AB8
mmc3_dat6
2332
2640
2752
2255
CFG_MMC3_DAT6_IN
-
vin5a_hsy
nc0
AB5
mmc3_dat7
1799
2927
1881
2844
CFG_MMC3_DAT7_IN
-
vin5a_vsyn
c0
D18
xref_clk0
681
0
824
0
CFG_XREF_CLK0_IN
vin6a_d0
-
E17
xref_clk1
21
0
0
0
CFG_XREF_CLK1_IN
vin6a_clk0
-
7.7
Display Subsystem – Video Output Ports
Three Display Parallel Interfaces (DPI) channels are available in DSS named DPI Video Output 1, DPI
Video Output 2 and DPI Video Output 3.
NOTE
The DPI Video Output i (i = 1 to 3) interface is also referred to as VOUTi.
Every VOUT interface consists of:
•
24-bit data bus (data[23:0])
•
Horizontal synchronization signal (HSYNC)
•
Vertical synchronization signal (VSYNC)
•
Data enable (DE)
•
Field ID (FID)
•
Pixel clock (CLK)
NOTE
For more information, see the Display Subsystem chapter of the Device TRM.
CAUTION
The I/O timings provided in this section are valid only if signals within a single
IOSET are used. The IOSETs are defined in Table 7-19 and Table 7-20.
CAUTION
The I/O Timings provided in this section are valid only for some DSS usage
modes when the corresponding Virtual I/O Timings or Manual I/O Timings are
configured as described in the tables found in this section.
CAUTION
All pads/balls configured as vouti_* signals are recommended to use slow slew
rate by setting the corresponding CTRL_CORE_PAD_*[SLEWCONTROL]
register field to SLOW (0b1). FAST slew setting is allowed, but results in faster
edge rates on the VOUTn bus, higher power/ground noise, and higher EMI
emissions compared to SLOW slew rate.



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