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TDA2SA Datasheet(PDF) 259 Page - Texas Instruments |
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TDA2SA Datasheet(HTML) 259 Page - Texas Instruments |
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259 / 427 page  259 TDA2SX, TDA2SG, TDA2SA TDA2HG, TDA2HV, TDA2HF, TDA2LF www.ti.com SPRS951F – DECEMBER 2015 – REVISED MAY 2019 Submit Documentation Feedback Product Folder Links: TDA2SX TDA2SG TDA2SA TDA2HG TDA2HV TDA2HF TDA2LF Timing Requirements and Switching Characteristics Copyright © 2015–2019, Texas Instruments Incorporated Table 7-41. McSPI3/4 IOSETs (continued) Signal IOSET1 IOSET2 IOSET3 IOSET4 IOSET5 IOSET6 BALL MUX BALL MUX BALL MUX BALL MUX BALL MUX BALL MUX spi4_d1 R4 8 G6 8 U7 7 AB9 2 AD6 1 - - spi4_d0 N9 8 F2 8 V6 7 AB3 2 AB8 1 - - spi4_cs0 P9 8 F3 8 U6 7 AA4 2 AB5 1 - - spi4_cs1 P4 8 P4 8 Y1 8 Y1 8 Y1 8 - - spi4_cs2 R3 8 R3 8 W9 8 W9 8 W9 8 - - spi4_cs3 T2 8 T2 8 V9 8 V9 8 V9 8 - - 7.15 Quad Serial Peripheral Interface (QSPI) The Quad SPI (QSPI) module is a type of SPI module that allows single, dual or quad read access to external SPI devices. This module has a memory mapped register interface, which provides a direct interface for accessing data from external SPI devices and thus simplifying software requirements. It works as a master only. There is one QSPI module in the device and it is primary intended for fast booting from quad-SPI flash memories. General SPI features: • Programmable clock divider • Six pin interface (DCLK, CS_N, DOUT, DIN, QDIN1, QDIN2) • 4 external chip select signals • Support for 3-, 4- or 6-pin SPI interface • Programmable CS_N to DOUT delay from 0 to 3 DCLKs • Programmable signal polarities • Programmable active clock edge • Software controllable interface allowing for any type of SPI transfer NOTE For more information, see the Quad Serial Peripheral Interface section of the Device TRM. CAUTION The IO Timings provided in this section are only valid for some QSPI usage modes when the corresponding Virtual IO Timings or Manual IO Timings are configured as described in the tables found in this section. CAUTION The IO Timings provided in this section are only valid when all QSPI Chip Selects used in a system are configured to use the same Clock Mode (either Clock Mode 0 or Clock Mode3). Table 7-42 and Table 7-43 present Timing and Switching Characteristics for Quad SPI Interface. |
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