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TDA2SA Datasheet(PDF) 257 Page - Texas Instruments |
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TDA2SA Datasheet(HTML) 257 Page - Texas Instruments |
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257 / 427 page ![]() spim _cs(IN) spi _sclk m (IN) spi _sclk m (IN) spi _ m d (OUT) spim _cs(IN) spi _sclk m (IN) spi _sclk m (IN) spi _ m d (OUT) Bit n-1 Bit n-2 Bit n-3 Bit n-4 Bit 0 Bit n-1 Bit n-2 Bit n-3 Bit 1 Bit 0 PHA=0 EPOL=1 POL=0 POL=1 POL=0 POL=1 PHA=1 EPOL=1 SS6 SS3 SS1 SS3 SS1 SS3 SS1 SS2 SS1 SS6 SS6 SS8 SS9 SS7 SS8 SS2 SS3 SS2 SS2 SS6 SS6 SS6 SS9 SPRS906_TIMING_McSPI_03 257 TDA2SX, TDA2SG, TDA2SA TDA2HG, TDA2HV, TDA2HF, TDA2LF www.ti.com SPRS951F – DECEMBER 2015 – REVISED MAY 2019 Submit Documentation Feedback Product Folder Links: TDA2SX TDA2SG TDA2SA TDA2HG TDA2HV TDA2HF TDA2LF Timing Requirements and Switching Characteristics Copyright © 2015–2019, Texas Instruments Incorporated (1) This timing applies to all configurations regardless of SPI_CLK polarity and which clock edges are used to drive output data and capture input data. (2) When operating the SPI interface in RX-only mode, the minimum Cycle time is 26ns (38.4MHz) (3) 62.5ns Cycle time = 16 MHz (4) P = SPICLK period. (5) PHA = 0; SPI_CLK phase is programmable with the PHA bit of the SPI_CH(i)CONF register. Figure 7-28. McSPI - Slave Mode Transmit |
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