TDA2SA datasheet(253/427 Pages) TI2

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TDA2SX, TDA2SG, TDA2SA

TDA2HG, TDA2HV, TDA2HF, TDA2LF

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SPRS951F – DECEMBER 2015 – REVISED MAY 2019

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Product Folder Links: TDA2SX TDA2SG TDA2SA TDA2HG TDA2HV TDA2HF TDA2LF

Timing Requirements and Switching Characteristics

(1) U = UART baud time = 1/programmed baud rate

Figure 7-25. UART Timing

7.14 Multichannel Serial Peripheral Interface (McSPI)

The McSPI is a master/slave synchronous serial bus. There are four separate McSPI modules (SPI1,

SPI2, SPI3, and SPI4) in the device. All these four modules support up to four external devices (four chip

selects) and are able to work as both master and slave.

The McSPI modules include the following main features:

•

Serial clock with programmable frequency, polarity, and phase for each channel

•

Wide selection of SPI word lengths, ranging from 4 to 32 bits

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Up to four master channels, or single channel in slave mode

•

Master multichannel mode:

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Full duplex/half duplex

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Transmit-only/receive-only/transmit-and-receive modes

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Flexible input/output (I/O) port controls per channel

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Programmable clock granularity

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SPI configuration per channel. This means, clock definition, polarity enabling and word width

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Power management through wake-up capabilities

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Programmable timing control between chip select and external clock generation

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Built-in FIFO available for a single channel.

•

Each SPI module supports multiple chip select pins spim_cs[i], where i = 1 to 4.

NOTE

For more information, see the Serial Communication Interface section of the device TRM.

NOTE

The McSPIm module (m = 1 to 4) is also referred to as SPIm.

CAUTION

The IO timings provided in this section are applicable for all combinations of

signals for SPI1 and SPI2. However, the timings are only valid for SPI3 and

SPI4 if signals within a single IOSET are used. The IOSETS are defined in the

Table 7-41.

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