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TDA2SA Datasheet(PDF) 250 Page - Texas Instruments |
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TDA2SA Datasheet(HTML) 250 Page - Texas Instruments |
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250 / 427 page  10 8 4 3 7 12 5 6 14 2 3 13 Stop Start Repeated Start Stop I2Ci_SDA I2Ci_SCL 1 11 9 250 TDA2SX, TDA2SG, TDA2SA TDA2HG, TDA2HV, TDA2HF, TDA2LF SPRS951F – DECEMBER 2015 – REVISED MAY 2019 www.ti.com Submit Documentation Feedback Product Folder Links: TDA2SX TDA2SG TDA2SA TDA2HG TDA2HV TDA2HF TDA2LF Timing Requirements and Switching Characteristics Copyright © 2015–2019, Texas Instruments Incorporated (1) The I2C pins SDA and SCL do not feature fail-safe I/O buffers. These pins could potentially draw current when the device is powered down. (2) A Fast-mode I2C-bus™ device can be used in a Standard-mode I2C-bus system, but the requirement tsu(SDA-SCLH)≥ 250 ns must then be met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line tr max + tsu(SDA-SCLH)= 1000 + 250 = 1250 ns (according to the Standard-mode I2C-Bus Specification) before the SCL line is released. (3) A device must internally provide a hold time of at least 300 ns for the SDA signal (referred to the VIHmin of the SCL signal) to bridge the undefined region of the falling edge of SCL. (4) The maximum th(SDA-SCLL) has only to be met if the device does not stretch the low period [tw(SCLL)] of the SCL signal. (5) Cb = total capacitance of one bus line in pF. If mixed with HS-mode devices, faster fall-times are allowed. Table 7-35. Timing Requirements for I2C HS-Mode (I2C3/4/5 Only)(1) NO. PARAMETER DESCRIPTION Cb = 100 pF MAX Cb = 400 pF (2) UNIT MIN MAX MIN MAX 1 tc(SCL) Cycle time, SCL 0.294 0.588 µs 2 tsu(SCLH-SDAL) Set-up time, SCL high before SDA low (for a repeated START condition) 160 160 ns 3 th(SDAL-SCLL) Hold time, SCL low after SDA low (for a repeated START condition) 160 160 ns 4 tw(SCLL) LOW period of the SCLH clock 160 320 ns 5 tw(SCLH) HIGH period of the SCLH clock 60 120 ns 6 tsu(SDAV-SCLH) Setup time, SDA valid vefore SCL high 10 10 ns 7 th(SCLL-SDAV) Hold time, SDA valid after SCL low 0 (3) 70 0 (3) 150 ns 13 tsu(SCLH-SDAH) Setup time, SCL high before SDA high (for a STOP condition) 160 160 ns 14 tw(SP) Pulse duration, spike (must be suppressed) 0 10 0 10 ns 15 Cb (2) Capacitive load for SDAH and SCLH lines 100 400 pF 16 Cb Capacitive load for SDAH + SDA line and SCLH + SCL line 400 400 pF (1) I2C HS-Mode is only supported on I2C3/4/5. I2C HS-Mode is not supported on I2C1/2. (2) For bus line loads Cb between 100 and 400 pF the timing parameters must be linearly interpolated. (3) A device must internally provide a Data hold time to bridge the undefined part between VIH and VIL of the falling edge of the SCLH signal. An input circuit with a threshold as low as possible for the falling edge of the SCLH signal minimizes this hold time. Figure 7-23. I2C Receive Timing |
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