TDA2SA datasheet(246/427 Pages) TI2

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GPMC_FCLK

gpmc_csi

gpmc_ben0

gpmc_

_ale

advn

gpmc_oen_ren

gpmc_wen

gpmc_ad[15:0]

DATA

GNF0

GNF1

GNF4

GNF6

GNF9

GNF3

GPMC_16

GPMC_FCLK

gpmc_csi

gpmc_ben0

gpmc_

_ale

advn

gpmc_oen_ren

gpmc_ad[15:0]

gpmc_waitj

DATA

GNF10

GNF13

GNF14

GNF15

GNF12

GPMC_15

246

TDA2SX, TDA2SG, TDA2SA

TDA2HG, TDA2HV, TDA2HF, TDA2LF

SPRS951F – DECEMBER 2015 – REVISED MAY 2019

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Product Folder Links: TDA2SX TDA2SG TDA2SA TDA2HG TDA2HV TDA2HF TDA2LF

Timing Requirements and Switching Characteristics

Figure 7-21. GPMC / NAND Flash - Data Read Cycle Timing(1)(2)(3)

(1) GNF12 parameter illustrates amount of time required to internally sample input Data. It is expressed in number of GPMC functional

clock cycles. From start of read cycle and after GNF12 functional clock cycles, input data will be internally sampled by active functional

clock edge. GNF12 value must be stored inside AccessTime register bits field.

(2) GPMC_FCLK is an internal clock (GPMC functional clock) not provided externally.

(3) In gpmc_csi, i = 0 to 7. In gpmc_waitj, j = 0 to 1.

Figure 7-22. GPMC / NAND Flash - Data Write Cycle Timing(1)

(1) In gpmc_csi, i = 0 to 7.

NOTE

To configure the desired virtual mode the user must set MODESELECT bit and

DELAYMODE bitfield for each corresponding pad control register.

The pad control registers are presented in Table 4-3 and described in Device TRM, Control

Module Chapter.

TDA2SA Datasheet(PDF) 246 Page - Texas Instruments

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