TDA2SA datasheet(249/427 Pages) TI2

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249

TDA2SX, TDA2SG, TDA2SA

TDA2HG, TDA2HV, TDA2HF, TDA2LF

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SPRS951F – DECEMBER 2015 – REVISED MAY 2019

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Product Folder Links: TDA2SX TDA2SG TDA2SA TDA2HG TDA2HV TDA2HF TDA2LF

Timing Requirements and Switching Characteristics

NOTE

For additional information on the Timer Module, see the Device TRM.

7.12 Inter-Integrated Circuit Interface (I2C)

The device includes 5 inter-integrated circuit (I2C) modules which provide an interface to other devices

compliant with Philips Semiconductors Inter-IC bus (I2C-bus™) specification version 2.1. External

components attached to this 2-wire serial bus can transmit/receive 8-bit data to/from the device through

the I2C module.

NOTE

Note that, on I2C1 and I2C2, due to characteristics of the open drain IO cells, HS mode is

not supported

NOTE

Inter-integrated circuit i (i=1 to 5) module is also referred to as I2Ci

NOTE

For more information, see the Multimaster High-Speed I2C Controller section of the Device

TRM.

Table 7-34, Table 7-35 and Figure 7-23 assume testing over the recommended operating conditions and

electrical characteristic conditions below.

Table 7-34. Timing Requirements for I2C Input Timings(1)

NO.

PARAMETER

DESCRIPTION

STANDARD MODE

FAST MODE

UNIT

MIN

MAX

MIN

MAX

tc(SCL)

Cycle time, SCL

2.5

µs

tsu(SCLH-SDAL)

Setup time, SCL high before SDA low (for a

repeated START condition)

4.7

0.6

µs

th(SDAL-SCLL)

Hold time, SCL low after SDA low (for a START

and a repeated START condition)

0.6

µs

tw(SCLL)

Pulse duration, SCL low

4.7

1.3

µs

tw(SCLH)

Pulse duration, SCL high

0.6

µs

tsu(SDAV-SCLH)

Setup time, SDA valid before SCL high

250

100(2)

th(SCLL-SDAV)

Hold time, SDA valid after SCL low

0(3)

3.45(4)

0(3)

0.9(4)

µs

tw(SDAH)

Pulse duration, SDA high between STOP and

START conditions

4.7

1.3

µs

tr(SDA)

Rise time, SDA

1000

20 + 0.1Cb

(5)

300(3)

tr(SCL)

Rise time, SCL

1000

20 + 0.1Cb

(5)

300(3)

tf(SDA)

Fall time, SDA

300

20 + 0.1Cb

(5)

300(3)

tf(SCL)

Fall time, SCL

300

20 + 0.1Cb

(5)

300(3)

tsu(SCLH-SDAH)

Setup time, SCL high before SDA high (for

STOP condition)

0.6

µs

tw(SP)

Pulse duration, spike (must be suppressed)

(5)

Capacitive load for each bus line

400

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