TDA2SA datasheet(254/427 Pages) TI2

254 / 427 page

254

TDA2SX, TDA2SG, TDA2SA

TDA2HG, TDA2HV, TDA2HF, TDA2LF

SPRS951F – DECEMBER 2015 – REVISED MAY 2019

www.ti.com

Submit Documentation Feedback

Product Folder Links: TDA2SX TDA2SG TDA2SA TDA2HG TDA2HV TDA2HF TDA2LF

Timing Requirements and Switching Characteristics

Table 7-39, Figure 7-26 and Figure 7-27 present Timing Requirements for McSPI - Master Mode.

Table 7-39. Timing Requirements for SPI - Master Mode (1)(8)

NO.

PARAMETER

DESCRIPTION

MODE

MIN

MAX

UNIT

SM1

tc(SPICLK)

Cycle time, spi_sclk (1) (2)

SPI1/2/3/4

20.8 (3)

SM2

tw(SPICLKL)

Typical Pulse duration, spi_sclk low (1)

0.5*P-1

(4)

SM3

tw(SPICLKH)

Typical Pulse duration, spi_sclk high (1)

0.5*P-1

(4)

SM4

tsu(MISO-SPICLK)

Setup time, spi_d[x] valid before spi_sclk active edge (1)

4.4

SM5

th(SPICLK-MISO)

Hold time, spi_d[x] valid after spi_sclk active edge (1)

3.9

SM6

td(SPICLK-SIMO)

Delay time, spi_sclk active edge to spi_d[x] transition (1)

SPI1

-4.27

4.27

SPI2

-4.32

4.32

SPI3

-5.37

4.23

SPI4

-3.81

4..41

SM7

td(CS-SIMO)

Delay time, spi_cs[x] active edge to spi_d[x] transition

SM8

td(CS-SPICLK)

Delay time, spi_cs[x] active to spi_sclk first edge (1)

MASTER_PHA0

(5)

B-4.6 (6)

MASTER_PHA1

(5)

A-4.6 (7)

SM9

td(SPICLK-CS)

Delay time, spi_sclk last edge to spi_cs[x] inactive (1)

MASTER_PHA0

(5)

A-4.6 (7)

MASTER_PHA1

(5)

B-4.6 (6)

(1) This timing applies to all configurations regardless of SPI_CLK polarity and which clock edges are used to drive output data and capture

input data.

(2) Related to the SPI_CLK maximum frequency.

(3) 20.8ns cycle time = 48MHz, 26ns cycle time = 38.4MHz

(4) P = SPICLK period.

(5) SPI_CLK phase is programmable with the PHA bit of the SPI_CH(i)CONF register.

(6) B = (TCS + 0.5) * TSPICLKREF * Fratio, where TCS is a bit field of the SPI_CH(i)CONF register and Fratio = Even

≥2.

(7) When P = 20.8 ns, A = (TCS + 1) * TSPICLKREF, where TCS is a bit field of the SPI_CH(i)CONF register. When P > 20.8 ns, A = (TCS

+ 0.5) * Fratio * TSPICLKREF, where TCS is a bit field of the SPI_CH(i)CONF register.

(8) The IO timings provided in this section are applicable for all combinations of signals for SPI1 and SPI2. However, the timings are only

valid for SPI3 and SPI4 if signals within a single IOSET are used. The IOSETs are defined in the following tables.

TDA2SA Datasheet(PDF) 254 Page - Texas Instruments

TDA2SA Datasheet(HTML) 254 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL