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TPD4F202 Datasheet(PDF) 3 Page - Texas Instruments |
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TPD4F202 Datasheet(HTML) 3 Page - Texas Instruments |
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3 / 16 page ![]() 5 Pin Configuration and Functions Figure 5-1. YFU Package 10-Pin DSBGA Top View Table 5-1. Pin Functions — TPD4F202 PIN TYPE DESCRIPTION NO. NAME A1 Ch1_In I/O ESD-protected channel, route to connector. Corresponds with CH1_Out. A3 Ch1_Out I/O ESD-protected channel, route to system. Corresponds with CH1_In. B2 GND G Ground C1 Ch2_In I/O ESD-protected channel, route to connector. Corresponds with CH2_Out. C3 Ch2_Out I/O ESD-protected channel, route to system. Corresponds with CH2_In. D1 Ch3_In I/O ESD-protected channel, route to connector. Corresponds with CH3_Out. D3 Ch3_Out I/O ESD-protected channel, route to system. Corresponds with CH3_In. E2 GND G Ground F1 Ch4_In I/O ESD-protected channel, route to connector. Corresponds with CH4_Out. F3 Ch4_Out I/O ESD-protected channel, route to system. Corresponds with CH4_In. www.ti.com TPD4F202, TPD6F202 SLLS800B – JUNE 2010 – REVISED MAY 2021 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 3 Product Folder Links: TPD4F202 TPD6F202 |
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