ADC12D040 datasheet(16/22 Pages) NSC

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Applications Information (Continued)

Where dev is the angular difference between the two signals

having a 180˚ relative phase relationship to each other (see

Figure 3). Drive the analog inputs with a source impedance

less than 100

Ω.

TABLE 1. Input to Output Relationship – Differential

Input

IN+

IN−

Binary Output

2’s Complement

Output

CM −

REF/2

CM +

REF/2

0000 0000 0000

1000 0000 0000

CM −

REF/4

CM +

REF/4

0100 0000 0000

1100 0000 0000

1000 0000 0000

0000 0000 0000

CM +

REF/4

CM −

REF/4

1100 0000 0000

0100 0000 0000

CM +

REF/2

CM −

REF/2

1111 1111 1111

0111 1111 1111

TABLE 2. Input to Output Relationship – Single-Ended

Input

IN+

IN−

Binary Output

2’s Complement

Output

CM −

REF

0000 0000 0000

1000 0000 0000

CM −

REF/2

0100 0000 0000

1100 0000 0000

1000 0000 0000

0000 0000 0000

CM +

REF/2

1100 0000 0000

0100 0000 0000

CM +

REF

1111 1111 1111

0111 1111 1111

1.3.1 Single-Ended Operation

Single-ended performance is lower than with differential in-

put signals. For this reason, single-ended operation is not

recommended. However, if single ended-operation is re-

quired and the resulting performance degradation is accept-

able, one of the analog inputs should be connected to the

d.c. mid point voltage of the driven input. The peak-to-peak

differential input signal should be twice the reference voltage

to maximize SNR and SINAD performance (Figure 2b).

For example, set V

REF to 1.0V, bias VIN− to 2.5V and drive

IN+ with a signal range of 1.5V to 3.5V.

Because very large input signal swings can degrade distor-

tion performance, better performance with a single-ended

input can be obtained by reducing the reference voltage

when maintaining a full-range output. Table 1 and Table 2

indicate the input to output relationship of the ADC12D040.

1.3.2 Driving the Analog Input

The V

IN+ and the VIN− inputs of the ADC12D040 consist of

an analog switch followed by a switched-capacitor amplifier.

The capacitance seen at the analog input pins changes with

the clock level, appearing as 8 pF when the clock is low, and

7 pF when the clock is high.

As the internal sampling switch opens and closes, current

pulses occur at the analog input pins, resulting in voltage

spikes at the signal input pins. As a driving amplifier attempts

to counteract these voltage spikes, a damped oscillation

may appear at the ADC analog inputs. The best amplifiers

for driving the ADC12D040 input pins must be able to react

to these spikes and settle before the switch opens and

another sample is taken. The LMH6702 LMH6628 and the

LMH6622, LMH6655 are good amplifiers for driving the

ADC12D040.

To help isolate the pulses at the ADC input from the amplifier

output, use RCs at the inputs, as can be seen in Figure 4

and Figure 5. These components should be placed close to

the ADC inputs because the input pins of the ADC is the

most sensitive part of the system and this is the last oppor-

tunity to filter that input.

For Nyquist applications the RC pole should be at the ADC

sample rate. The ADC input capacitance in the sample mode

should be considered when setting the RC pole. Setting the

pole in this manner will provide best SNR performance.

To obtain best SINAD and ENOB performance, reduce the

RC time constant until SNR and THD are numerically equal

to each other. To obtain best distortion and SFDR perfor-

mance, eliminate the RC altogether.

For undersampling applications, RC pole should be set at

about 1.5 to 2 times the maximum input frequency to main-

tain a linear delay response.

Note that the ADC12DL040 is not designed to operate with

single-ended inputs. However, doing so is possible if the

degraded performance is acceptable. See Section 1.3.1.

Figure 4 shows a narrow band application with a transformer

used to convert single-ended input signals to differential.

Figure 5 shows the use of a fully differential amplifier for

single-ended to differential conversion.

20046012

FIGURE 3. Angular Errors Between the Two Input

Signals Will Reduce the Output Level or Cause

Distortion

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