IP80C88 datasheet(13/38 Pages) INTERSIL

13 / 38 page

FN2949.4

February 22, 2008

To be responded to, INTR must be present (HIGH) during

the clock period preceding the end of the current instruction

or the end of a whole move for a block type instruction. INTR

may be removed anytime after the falling edge of the first

INTA signal. During interrupt response sequence, further

interrupts are disabled. The enable bit is reset as part of the

response to any interrupt (INTR, NMI, software interrupt, or

single step). The FLAGS register, which is automatically

pushed onto the stack, reflects the state of the processor

prior to the interrupt. The enable bit will be zero until the old

FLAGS register is restored, unless specifically set by an

instruction.

During the response sequence (see Figure 7), the processor

executes two successive (back-to-back) interrupt

acknowledge cycles. The 80C88 emits to LOCK signal

(maximum mode only) from T2 of the first bus cycle until T2

of the second. A local bus “hold” request will not be honored

until the end of the second bus cycle. In the second bus

cycle, a byte is fetched from the external interrupt system

(e.g., 82C59A PIC) which identifies the source (type) of the

interrupt. This byte is multiplied by four and used as a

pointer into the interrupt vector lookup table.

An INTR signal left HIGH will be continually responded to

within the limitations of the enable bit and sample period.

INTR may be removed anytime after the falling edge of the

first INTA signal. The interrupt return instruction includes a

flags pop which returns the status of the original interrupt

enable bit when it restores the flags.

Halt

When a software HALT instruction is executed, the

processor indicates that it is entering the HALT state in one

of two ways, depending upon which mode is strapped. In

minimum mode, the processor issues ALE, delayed by one

clock cycle, to allow the system to latch the halt status. Halt

status is available on IO/M, DT/R, and SS0. In maximum

mode, the processor issues appropriate HALT status on S2,

S1 and S0, and the 82C88 bus controller issues one ALE.

The 80C88 will not leave the HALT state when a local bus

hold is entered while in HALT. In this case, the processor

reissues the HALT indicator at the end of the local bus hold.

An interrupt request or RESET will force the 80C88 out of

the HALT state.

Read/Modify/Write (Semaphore) Operations Via

LOCK

The LOCK status information is provided by the processor

when consecutive bus cycles are required during the

execution of an instruction. This allows the processor to

perform read/modify/write operations on memory (via the

“exchange register with memory” instruction), without

another system bus master receiving intervening memory

cycles. This is useful in multiprocessor system

configurations to accomplish “test and set lock” operations.

The LOCK signal is activated (LOW) in the clock cycle

following decoding of the LOCK prefix instruction. It is

deactivated at the end of the last bus cycle of the instruction

following the LOCK prefix. While LOCK is active, a request

on a RQ/GT pin will be recorded, and then honored at the

end of the LOCK.

External Synchronization Via TEST

As an alternative to interrupts, the 80C88 provides a single

software-testable input pin (TEST). This input is utilized by

executing a WAIT instruction. The single WAIT instruction is

repeatedly executed until the TEST input goes active (LOW).

The execution of WAIT does not consume bus cycles once

the queue is full.

If a local bus request occurs during WAIT execution, the

80C88 three-states all output drivers while inputs and I/O

pins are held at valid logic levels by internal bus-hold

circuits. If interrupts are enabled, the 80C88 will recognize

interrupts and process them when it regains control of the

bus.

Basic System Timing

In minimum mode, the MN/MX pin is strapped to VCC and

the processor emits bus control signals (RD, WR, IO/M, etc.)

directly. In maximum mode, the MN/MX pin is strapped to

GND and the processor emits coded status information

which the 82C88 bus controller uses to generate

MULTIBUS

™ compatible bus control signals.

System Timing - Minimum System

The read cycle begins in T1 with the assertion of the address

latch enable (ALE) signal (see Figure 5). The trailing (low

going) edge of this signal is used to latch the address

information, which is valid on the address data bus (ADO-

AD7) at this time, into the 82C82/82C83 latch. Address lines

A8 through A15 do not need to be latched because they

remain valid throughout the bus cycle. From T1 to T4 the

IO/M signal indicates a memory or I/O operation. At T2 the

address is removed from the address data bus and the bus

is held at the last valid logic state by internal bus-hold

devices. The read control signal is also asserted at T2. The

read (RD) signal causes the addressed device to enable its

data bus drivers to the local bus. Some time later, valid data

FIGURE 7. INTERRUPT ACKNOWLEDGE SEQUENCE

ALE

LOCK

INTA

AD0-

TYPE

AD7

VECTOR

80C88

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