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DS3182 Datasheet(PDF) 18 Page - Dallas Semiconductor |
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DS3182 Datasheet(HTML) 18 Page - Dallas Semiconductor |
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18 / 400 page  DS3181/DS3182/DS3183/DS3184 18 • Detection of RDI, AIS, DS3 idle signal, loss of signal (LOS), severely errored framing event (SEFE), change of frame alignment (COFA), receipt of B3ZS/HDB3 code words, DS3 application ID bit, DS3 M23/C-bit format mismatch, G.751 national bit, and G.832 RDI (FERF), payload type, and timing marker bits • HDLC port for DS3 path maintenance data link (PMDL), G.751 national bit or G.832 NR or GC channels • FEAC port for DS3 FEAC channel • 16-byte Trail Trace Buffer port for G.832 trail access point identifier • DS3 M23 C bits and stuff bits configurable as payload or overhead, stored in registers for software inspection • Most framing overhead fields presented on the receive overhead port • Support for internal and external subrate DS3/E3 control (Fractional DS3/E3) 3.4 Receive PLCP Framer Features • PLCP frame synchronization • C1 cycle/stuff counter interpretation • Detection of out of frame (OOF), BIP-8 errors, FEBE and RAI (Yellow Signal) • Frame timing can be presented on the GPIO2 output pin or used as the transmit PLCP reference • All path overhead fields presented on the PLCP receive overhead port • HDLC port for data link messages on F1, M1 or M2 bytes • Trail Trace port for trace messages on F1 byte 3.5 Receive Cell Processor Features • HEC-based cell delineation within the DS3/E3 frame, the PLCP frame, an externally defined frame, or the entire line bandwidth • Cell descrambling using the self-synchronizing scrambler (x 43+1) for ATM over DS3/E3 • Distributed Sample Scrambler (DSS) for clear-channel ATM (cell-based physical layer) • HEC error detection and correction; HEC discard • Filtering of idle, unassigned and/or invalid cells (provisionable) • Header pattern comparison vs. 32-bit header pattern and mask registers; counting of matching or non- matching cells; discard of matching or non-matching cells • Four-cell Receive FIFO • Controls include enables/disables/settings for: cell processing, coset polynomial addition, error correction, erred cell extraction, cell descrambling, idle/unassigned/invalid cell filtering, header pattern match counting/discarding, LCD integration time • Status fields include: out of cell delineation (OCD), loss of cell delineation (LCD) and receipt of idle, unassigned, invalid, erred, corrected or header-pattern-match cells • Performance monitoring counters for forwarded cells, corrected cells, uncorrectable cells, header pattern match/no-match cells, and filtered idle/unassigned/invalid cells • Octet alignment option for externally defined frame formats 3.6 Receive Packet Processor Features • Packet descrambling using the self-synchronizing scrambler (x 43+1) • Flag detection, packet delineation, and inter-frame fill discard (flags and all-ones) • Packet abort detection and accumulation • Bit or octet destuffing • FCS checking (16-bit or 32-bit), error accumulation, and FCS discard • Packet size checking vs. programmable minimum and maximum size registers • Abort declaration for packets with non-integral number of bytes • Controls include enables/disables/settings for: packet processing, descrambling, 16/32-bit FCS, filtering of FCS erred packets, FCS discard, minimum/maximum packet size • Status fields include: receipt of FCS erred packet, aborted packet, size violation packet, non-integer-length packets • Performance monitoring counters for forwarded packets, forwarded bytes, aborted bytes, FCS erred packets, aborted packets, size violation packets (min, max, non-integer-length) • Octet alignment with octet destuffing option for externally defined frame formats |
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