DS3182 datasheet(21/400 Pages) DALLAS

21 / 400 page

DS3181/DS3182/DS3183/DS3184

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Terminates the Path Maintenance Data Link in DS3 C-bit Parity mode and optionally the G.751 Sn bit or the

G.832 NR or GC channels or PLCP F1, M1 or M2 bytes

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RX data is forced to all ones during LOS, LOF and AIS detection to eliminate false packets

3.19 FEAC Controller Features

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Each port has a dedicated FEAC controller for DS3/E3 link management

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Designed to handle multiple FEAC code words without Host intervention

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Receive FEAC automatically validates incoming code words and stores them in a 4-byte FIFO

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Transmit FEAC can be configured to send one codeword, one codeword continuously, or two different code

words back-to-back to send DS3 Line Loopback commands

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Terminates the FEAC channel in DS3 C-Bit Parity mode and optionally the Sn bit in E3 mode

3.20 Trail Trace Buffer Features

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Each port has a dedicated Trail Trace Buffer for E3-G.832 or DS3/E3 PLCP link management

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Extraction and storage of the incoming G.832 or PLCP trail access point identifier in a 16-byte receive register

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Insertion of the outgoing trail access point identifier from a 16-byte transmit register

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Receive trace identifier unstable status indication

3.21 Bit Error Rate Tester (BERT) Features

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Each port has a dedicated BERT tester

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Generation and detection of pseudo-random patterns and repetitive patterns from 1 to 32 bits in length

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Pattern insertion/extraction in PLCP payload, DS3/E3 payload, DS3/E3 fractional payload or entire data stream

to and from the line interface

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Large 24-bit error counter allows testing to proceed for long periods without host intervention

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Errors can be inserted in the generated BERT patterns for diagnostic purposes (single bit errors or specific bit-

error rates)

3.22 Loopback Features

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Analog interface loopback – ALB (transmit to receive)

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Line facility loopback – LLB (receive to transmit) with optional transmission of unframed all-one AIS payload

toward system/trunk interface

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Framer diagnostic loopback – DLB (transmit to receive) with automatic transmission of DS3 AIS or unframed

all-one AIS signal toward line/tributary interface(s)

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DS3/E3 framer payload loopback – PLB (receive to transmit) with optional transmission of unframed all-one

AIS payload toward system/trunk interface

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System interface loopback – SLB (transmit to receive)

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Simultaneous line facility loopback and framer diagnostic loopback

3.23 Microprocessor Interface Features

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Multiplexed or non-multiplexed address bus modes

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8 or 16-bit data bus modes

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Byte swapping option in 16-bit data bus mode

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Read/Write and Data Strobe modes

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Ready handshake output signal

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Global reset input pin

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Global interrupt output pin

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Two programmable I/O pins per port

3.24 Subrate Features (Fractional DS3/E3)

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Independent per-port built-in support for subrate DS3 or E3

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Independent subrate operation for both RX and TX data paths

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Subrate operation for each channel is totally independent from the other channels’ operation, i.e. all subrate

functions within the device are mutually exclusive

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Three distinct subrate algorithms:

DS3182 Datasheet(PDF) 21 Page - Dallas Semiconductor

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