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GD32H757ZMT7 Datasheet(PDF) 93 Page - GigaDevice Semiconductor (Beijing) Inc. |
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GD32H757ZMT7 Datasheet(HTML) 93 Page - GigaDevice Semiconductor (Beijing) Inc. |
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93 / 151 page  GD32H757xx Datasheet 92 Table 4-9. System level ESD and EFT characteristics(1) Symbol Description Conditions Package Class Level VESD Contact / Air mode high voltage stressed on few special I/O pins VDD = 3.3 V, TJ = 25 °C, fHCLK = 600 MHz IEC 61000-4-2 BGA176 CD 8kV AD 15kV 4A LQFP176 CD 8kV AD 15kV 4A VEFT Fast transient high voltage burst stressed on Power and GND VDD = 3.3 V, TJ = 25 °C, fHCLK = 600 MHz IEC 61000-4-4 BGA176 4kV 4A LQFP176 4kV 4A (1) Value guaranteed by characterization, not 100% tested in production. EMI (Electromagnetic Interference) emission test result is given in the Table 4-10. EMI characteristics(1) , The electromagnetic field emitted by the device are monitored while an application, executing EEMBC code, is running. The test is compliant with SAE J1752-3:2017 standard which specifies the test board and the pin loading. Table 4-10. EMI characteristics(1) Symbol Parameter Conditions Package Mode Max vs. [fHXTAL/fHCLK] 8/600 MHz Unit 0.1- 30MHz 30- 130MHz 130MHz- 1GHz 1-3GHz SEMI Peak level VDD = 3.6 V, TJ = +25 °C, fHCLK = 600 MHz, conforms to SAE J1752- 3:2017 BGA176 LDO supply 2.55 7.55 6.17 6.70 dB μV LQFP176 LDO supply 4.00 7.36 12.64 6.86 (1) Value guaranteed by characterization, not 100% tested in production. Component level ESD include HBM (Human body model, according to ANSI/ESDA/JEDEC JS-001) and CDM (ANSI/ESDA/JEDEC JS-002), that ESD field events during manufacturing in an ESD protected area, such as PCB assembly/repair, IC assembly/test and Fab environment. The ESD protected area (EPA) has many measures, for instance ESD protective packaging, grounding person wrist strap to ground (or flooring/footwear), grounded work surface and ionizer. Static latch-up (LU, according to JEDEC78) test is based on the two measurement methods, I/O current injection value (I-test) and power supply over-voltage value. |
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