GD32H757ZMT7 datasheet(126/151 Pages) GIGADEVICE

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GD32H757xx Datasheet

125

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

tSCK(H)

SCK clock high time, even

division

—

t(CK)/2

—

t(CK)/2+1

SCK clock high time, odd

division

—

(n/2)*t(CK)/

(n+1)

—

(n/2)*t(CK)/

(n+1)+1

tSCK(L)

SCK clock low time, even

division

—

t(CK)/2–1

—

t(CK)/2

SCK clock low time, odd

division

—

(n/2+1)*t(

CK)

(n+1)–1

—

(n/2+1)*t(

CK)

/(n+1)

tV(MO)

Data output valid time

—

0.5

tH(MO)

Data output hold time

—

tSU(MI)

Data input setup time

—

3.0

—

tH(MI)

Data input hold time

—

1.5

—

DTR mode(no DQS)

fSCK

SCK clock frequency

—

MHz

tSCK(H)

SCK clock high time, even

division

—

t(CK)/2

—

t(CK)/2+1

SCK clock high time, odd

division

—

(n/2)*t(CK)/

(n+1)

—

(n/2)*t(CK)/

(n+1)+1

tSCK(L)

SCK clock high time, even

division

—

t(CK)/2–1

—

t(CK)/2

SCK clock high time, odd

division

—

(n/2+1)*t(

CK)

(n+1)–1

—

(n/2+1)*t(

CK)

/(n+1)

tVR(SO)

tVF(SO)

Data output valid time

DHQC = 0

—

DHQC = 1, Prescaler =

1,2 ...

—

tpclk/4

+ 1

tpclk/4+1.2

5 (6)

tHR(SO)

tHF(SO)

Data output hold time

DHQC = 0

4.5

—

DHQC = 1, Prescaler =

1,2 ...

tpclk/4

—

tSUR(SI)

tSUF(SI)

Data input setup time

—

3.0

—

tHR(SI)

tHF(SI)

Data input hold time

—

1.50

—

(1)

Value guaranteed by characterization, not 100% tested in production.

GD32H757ZMT7 Datasheet(PDF) 126 Page - GigaDevice Semiconductor (Beijing) Inc.

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