TMP442 datasheet(20/63 Pages) TI2

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7.5.2 I2C and SMBus Interface

The TMP4719 has a standard bidirectional I2C interface that can be configured or read by a controller. Each

target on the I2C bus has a specific device address to differentiate between other target devices that are on

the same I2C bus. Target devices require configuration upon start-up to set the behavior of the device. This

is typically done when the controller accesses internal register maps of the target, which have unique register

addresses. A device can have one or multiple registers where data is stored, written, or read. The TMP4719

includes 50ns glitch suppression filters, allowing the device to coexist on I3C mixed bus.

The physical I2C interface consists of the serial clock (SCL) and serial data (SDA) lines. Both SDA and SCL

lines must be connected to a bus supply through a pullup resistor. The size of the pullup resistor is determined

by the amount of capacitance on the I2C lines and communication speed. See also the I2C Bus Pullup Resistor

Calculation application note. Data transfer can be initiated only when the bus is idle. A bus is considered idle if

both SDA and SCL lines are high after a STOP condition (see Figure 7-10 and Figure 7-11). See the Writes and

Reads sections for detailed procedures on how the controller can access the TMP4719.

SCL

SDA

Data Transfer

START

Condition

STOP

Condition

Figure 7-10. Definition of Start and Stop Conditions

TMP4719

SBOSAJ7A – OCTOBER 2025 – REVISED DECEMBER 2025

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TMP442 Datasheet(PDF) 20 Page - Texas Instruments