IP113F
Preliminary Data Sheet
The basic MII registers (continued)
MII
NAME
R/W
DESCRIPTION
DEFAULT
MII control register (address 00h)
0.9
Restart Auto-
Negotiation
RW
1 = re-starting Auto-Negotiation
0 = Auto-Negotiation re-start complete
Setting this bit to logic high will cause IP113F to
restart an Auto-Negotiation cycle, but depend on the
value of bit 0.12 (Auto-Negotiation Enable). If bit
0.12 is cleared then this bit has no effect, and
change to Read Only. When an Auto-Negotiation
cycle is being processed, write 0 into this bit has no
effect. This bit is self-clearing after Auto-Negotiation
process is completed.
0
0.8
Duplex mode
R/W
1 = full duplex
0 = half duplex
It is valid only if bit 0.12 is set to be 0.
Pin(1)
0.7
Collision test enable
R/W
1 = enable the collision test
0 = disable the collision test
If setting this bit to logic 1, when MII TXEN signal is
asserted, IP113F will assert the MII COL signal
within 512BT (Bit Time, depend on 10Mbps or
100Mbps). When MII TXEN is de-asserted, then
TP110 will assert MII COL signal within 4BT.
Clearing this bit to logic 0 for normal operation
0
0[6:0]
Reserved
R/W
Write as 0, ignore on read
-
Confidential.
26/46
Aug. 20, 2003
Copyright © 2003, IC Plus Corp.
IP113F-DS-R02
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
