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64WQ Datasheet(PDF) 34 Page - Numonyx B.V |
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64WQ Datasheet(HTML) 34 Page - Numonyx B.V |
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34 / 46 page  32WQ and 64WQ Family with Asynchronous RAM Datasheet November 2007 34 Order Number: 251407-13 32WQ and 64WQ Family with Asynchronous RAM 16.0 SRAM Operations 16.1 Power-up Sequence and Initialization The SRAM functionality and reliability are independent of the power-up sequence and power-up slew rate of the core S-VCC. Any power-up sequence and power-up slew rate is possible under use conditions. SRAM reliability is also independent of the power- down sequence and power-down slew rate of the core S-VCC. 16.2 Data Retention Mode Table 17: SRAM Data Retention Operation Symbol Parameter Min Max Unit Notes tSDR Data Retention Set-up Time 0 – ns tRDR Data Retention Recovery Time tRC –ns 1 Note: 1. tRC is defined in Table 9, “SRAM AC Characteristics” on page 20. Figure 12: SRAM Data Retention Operation Waveform—S-CS1# Controlled S-V CC S-V CCmin S-V IHmin V DR V SS t SDR Data Retention Mode t RDR S-CS1# |
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