64WQ datasheet(14/46 Pages) NUMONYX

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32WQ and 64WQ Family with Asynchronous RAM

Datasheet

November 2007

Order Number: 251407-13

32WQ and 64WQ Family with Asynchronous RAM

4.2

Signal Descriptions

Table 3:

Signal Descriptions (Sheet 1 of 2)

Symbol

Type

Name and Function

A[21:0]

Input

ADDRESS INPUTS: Inputs for all die addresses during read and write operations. Addresses are

internally latched during write operations.

• 4-Mbit: A[17:0]

• 8-Mbit: A[18:0]

• 16-Mbit: A[19:0]

• 32-Mbit: A[20:0]

• 64-Mbit: A[21:0]

A0 is the lowest-order word address.

A[25:22] denote high-order addresses reserved for future device densities

D[15:0]

Input/

Output

DATA INPUTS/OUTPUTS: Inputs data and commands during write cycles; outputs data during read

cycles. Data signals float when the device or its outputs are deselected. Data are internally latched

during writes.

CLK

Input

FLASH CLOCK: CLK synchronizes the selected flash die to the memory bus frequency in

synchronous-read mode. During synchronous read operations, the initial address is latched on the

rising edge of ADV#, or the rising/ falling edge of CLK when ADV# is low, whichever occurs first.

CLK is only used in synchronous-read mode. Refer to the flash discrete product datasheet for

information on how to use this signal in asynchronous-read mode.

ADV#

Input

FLASH ADDRESS VALID: Low-true; During synchronous read operations, the initial address is

latched on the rising edge of ADV#, or the rising/ falling edge of CLK when ADV# is low, whichever

occurs first.

Refer to the flash discrete product datasheet for information on how to use this signal in

asynchronous-read mode.

WAIT

Output

FLASH WAIT: When asserted, WAIT indicates invalid data from the selected flash die on D[15:0].

WAIT is High-Z whenever the flash die is deselected (CE# = VIL). WAIT is not gated by OE#.

WAIT is only used in synchronous array-read mode. Refer to the flash discrete product datasheet for

information on how to use this signal in asynchronous-read mode.

F[3:1]-CE#

Input

FLASH CHIP ENABLE: Low-true; CE#-low selects the associated flash memory die. When asserted,

flash internal control logic, input buffers, decoders, and sense amplifiers are active. When deasserted,

the associated flash die is deselected; power is reduced to standby levels, data and WAIT outputs are

placed in High-Z.

F1-CE# selects flash die #1; F2-CE# selects flash die #2 and is RFU on combinations with only one

flash die. F3-CE# selects flash die #3 and is RFU on SCSP combinations with only one or two flash

die.

S-CS1#

S-CS2

Input

SRAM CHIP SELECTS: When both SRAM chip selects are asserted, SRAM internal control logic, input

buffers, decoders, and sense amplifiers are active. When either/both SRAM chip selects are

deasserted (S-CS1# = VIH and/or S-CS2 = VIL), the SRAM is deselected and its power is reduced to

standby levels.

S-CS1# and S-CS2 are only available on SCSP combinations with SRAM die.

P[2:1]-CS#

Input

PSRAM CHIP SELECTS: Low-true; When asserted, PSRAM internal control logic, input buffers,

decoders, and sense amplifiers are active. When deasserted, the PSRAM is deselected and its power

is reduced to standby levels.

P1-CS# selects PSRAM die #1 and is available only on SCSP combinations with PSRAM die. This ball is

RFU on SCSP combinations without PSRAM. P2-CS# selects PSRAM die #2 and is available only on

SCSP combinations with two PSRAM die. This ball is RFU on SCSP combinations without PSRAM or

with a single PSRAM.

F[2:1]-OE#

Input

FLASH OUTPUT ENABLE: Low-true; OE#-low enables the flash output buffers. OE#-high disables

the flash output buffers, and places the flash outputs in High-Z.

F1-OE# controls the outputs of flash die #1; F2-OE# controls the outputs of flash die #2 and #3, and

is available only on SCSP combinations with two or three flash die and is RFU on SCSP combinations

with only one flash die.

R-OE#

Input

RAM OUTPUT ENABLE: Low-true; R-OE#-low enables the RAM output buffers. R-OE#-high disables

the RAM output buffers, and places the RAM outputs in High-Z.

R-OE# is only available on SCSP combinations with RAM die.

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