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64WQ Datasheet(PDF) 32 Page - Numonyx B.V |
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64WQ Datasheet(HTML) 32 Page - Numonyx B.V |
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32 / 46 page ![]() 32WQ and 64WQ Family with Asynchronous RAM Datasheet November 2007 32 Order Number: 251407-13 32WQ and 64WQ Family with Asynchronous RAM Read Flash#1 and #2 must be in High-Z LH L H L PSRAM DOUT 1, 5, 2 Write LH H L L PSRAM DIN 5, 2 Output Disable Any flash mode allowed L HHH X PSRAM High-Z 6, 2 Standby H H X X X PSRAM High-Z 6, 2 Deep Power- Down HL X X X PSRAM High-Z 6, 9, 2 Notes: 1. For asynchronous read operation, all die may be simultaneously selected, but may not simultaneously drive the memory bus. For synchronous burst-mode reads, only two die (one flash and the PSRAM) may be simultaneously selected. 2. WAIT is only valid during synchronous flash reads. WAIT is driven if F-CE# is asserted. 3. F1-CE# for Flash Die#1, F2-CE# for Flash Die#2. F1-OE# is for Flash Die#1, F2-OE# for Flash Die#2. 4. For either flash die, F[2:1]-OE# and F-WE# should never be asserted simultaneously. If done so on a particular flash die, F[2:1]-OE# will override F-WE#. 5. For PSRAM, R-OE# and R-WE# should never be asserted simultaneously. 6. X can be VIL or VIH for inputs, VPPL,VPPH or VPPLK for F-VPP. 7. Flash CFI query and status register accesses use D[7:0] only, all other reads use D[15:0]. 8. Refer to W30/W18 datasheet for Valid DIN during flash writes. 9. Deep power-down is not applicable to 38F2020W0ZTQ1, 38F2020W0ZBQ1, 38F2030W0YTQ1, 38F2030W0YBQ1, 38F2030W0ZTQ2, 38F2030W0ZBQ2, 38F1030W0ZTQ0, 38F1030W0ZBQ0. Table 16: Flash + PSRAM Bus Operations Mode |
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