NXP Semiconductors

PCA9601

Dual bidirectional bus buffer

PCA9601

SX

local master bus

VCCM

SCL

MASTER

I2C-BUS

Cb

buffered bus

wiring capacitance

Cm

master bus

capacitance

Rm

GND (0 V)

VCCB

buffered expansion bus

TX/RX

TX/RX

Rb

002aae881

Effective delay of SCL at master: 115 + (Rm × Cm) + (0.7 × Rb × Cb) (ns).

C = F; R = Ω.

Figure 17. Rising edge of SCL at master is delayed (clock stretch) by buffer and bus rise times

PCA9601

PCA9601

SDA

SX

local master bus

VCCM

SDA

MASTER

I2C-BUS

Cs

slave bus

capacitance

Cb

buffered bus

wiring capacitance

Cm

master bus

capacitance

Rm

GND (0 V)

VCCB

buffered expansion bus

TX/RX

TX/RX

SX

Rb

Rs

I2C-BUS

SLAVE

VCCS

remote slave bus

002aae882

Effective delay of SDA at master: 115 + 0.2(Rs × Cs) + 0.7[(Rb × Cb) + (Rm × Cm)] (ns).

C = F; R = Ω.

Figure 18. Rising edge of SDA at slave is delayed by the buffers and bus rise times

Figure 16, Figure 17, and Figure 18 show the PCA9601 used to drive extended bus

wiring with relatively large capacitances linking two I2C-bus nodes. It includes simplified

expressions for making the relevant timing calculations for 3.3 V or 5 V operation.

Because the buffers and the wiring introduce timing delays, it may be necessary to

decrease the nominal SCL frequency. In most cases the actual bus frequency will be

lower than the nominal Master timing due to bit-wise stretching of the clock periods.

The delay factors involved in calculation of the allowed bus speed are:

A: The propagation delay of the master signal through the buffers and wiring to the slave.

The important delay is that of the falling edge of SCL because this edge ‘requests’ the

data or acknowledge from a slave. See Figure 16.

PCA9601

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Product data sheet

Rev. 3.1 — 4 January 2022

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