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DAC39RF10 Datasheet(PDF) 218 Page - Texas Instruments |
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DAC39RF10 Datasheet(HTML) 218 Page - Texas Instruments |
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218 / 232 page  Return Via for high speed clock rou ng Figure 9-26. Return Vias for High Speed Clock Near Clock Generator 9. Pay particular attention to potential coupling between JESD204x data input routing and the analog output routing. Switching noise from the JESD204x inputs can couple into the analog output traces and show up as wideband noise due to the high bandwidth of the DAC. Route the Serdes JESD204x data inputs on a separate layer, if possible, from the DAC output traces to avoid noise coupling, see Figure 9-27 and Figure 9-28 as examples. DAC39RF10-SP, DAC39RF10-SEP DAC39RFS10-SP, DAC39RFS10-SEP SBAS932A – MARCH 2024 – REVISED FEBRUARY 2026 www.ti.com 218 Submit Document Feedback Copyright © 2026 Texas Instruments Incorporated Product Folder Links: DAC39RF10-SP DAC39RF10-SEP DAC39RFS10-SP DAC39RFS10-SEP |
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