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DAC39RF10 Datasheet(PDF) 8 Page - Texas Instruments |
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DAC39RF10 Datasheet(HTML) 8 Page - Texas Instruments |
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8 / 232 page ![]() Table 5-1. Pin Functions (continued) PIN TYPE(1) DESCRIPTION NAME NO. SYNC J4 O JESD204C SYNC output, active low. TXEN0 D5 I Transmit enable for channel A active high input. This pin must be enabled using register USE_TX_EN0. The DAC output is forced to midcode (0x0000 in 2's complement) when transmission is disabled. Internal pullup. TXEN1 D4 I Transmit enable for channel B active high input. This pin must be enabled using register USE_TX_EN1. The DAC output is forced to midcode (0x0000 in 2's complement) when transmission is disabled. Internal pullup. ANALOG FUNCTIONS ATEST N6 O Analog test pin for TI use. Must be left disconnected. EXTREF J15 I/O Reference voltage output or input, determined by the EXTREF_EN register field. If the internal reference is used, the ball must be tied through 0.1uF to AGND. RBIAS- H16 O Full-scale output current bias is set by the resistor tied from this terminal to RBIAS+. RBIAS+ J16 O Full-scale output current bias is set by the resistor tied from this terminal to RBIAS-. RTEST M5 O TI use only. Tie to AGND. POWER SUPPLIES VDDA18A G14 H14 I 1.8V supply voltage for DAC channel A. Can be combined with VDDA18B, but can degrade channel-to-channel crosstalk (XTALK). VDDA18B J14 K14 I 1.8V supply voltage for DAC channel B. Can be combined with VDDA18A, but can degrade channel-to-channel crosstalk (XTALK). VDDCLK10 F11 H11 J11 L11 E12 M12 I 1V supply voltage for internal sampling clock distribution path. Noise or spurs on this supply can degrade phase noise performance. Recommended to separate from VDDDIG and VDDA for best performance. VDDCLK18 H12 H13 I 1.8V supply voltage for clock (CLK+/–) input buffer. Noise or spurs on this supply can degrade phase noise performance. VDDDIG F7 H7 J7 L7 N7 G8 K8 M8 I 1V supply voltage for digital block. Recommended to separate from VDDA and VDDCLK for best performance. VDDEA F8 F9 I 1V supply voltage for channel A DAC encoder. Recommended to separate from VDDDIG for best performance. Can be combined with VDDEB. VDDEB L8 L9 I 1V supply voltage for channel B DAC encoder. Recommended to separate from VDDDIG for best performance. Can be combined with VDDEA. VDDIO D9 E9 I 1.8V supply for CMOS input and output terminals. VDDLA F10 H10 I 1V supply for DAC analog latch for channel A. Separate from VDDLB for best channel-to- channel crosstalk (XTALK). Must be separated from VDDDIG for best performance. VDDLB J10 L10 I 1V supply for DAC analog latch for channel B. Separate from VDDLA for best channel-to- channel crosstalk (XTALK). Must be separated from VDDDIG for best performance. VDDR18 K4 L4 M4 N4 I 1.8V Supply voltage for SerDes receivers. VDDSYS18 J12 J13 I 1.8V supply voltage for SYSREF (SYSREF+/–) input buffer. Can be combined with VDDCLK18 when SYSREF is disabled during normal operation. This supply must be separate from VDDCLK18 when SYSREF is run continuously during operation to avoid noise and spur coupling and reduced phase noise performance. VDDT C3 D3 F3 G3 K3 L3 N3 P3 C4 P4 C5 H5 J5 P5 G6 K6 M6 C7 P7 C8 P8 I 1V Supply voltage for SerDes termination. VEEAM18 C11 D11 C12 D12 C13 D13 I –1.8V supply voltage for DAC current source bias for channel A. Can be combined with VEEBM18, but can degrade channel-to-channel crosstalk (XTALK). VEEBM18 N11 P11 N12 P12 N13 P13 I –1.8V supply voltage for DAC current source bias for channel B. Can be combined with VEEAM18, but can degrade channel-to-channel crosstalk (XTALK). VQPS N9 P9 I TI use only. Can be tied to DGND during normal operation. GROUNDS DAC39RF10-SP, DAC39RF10-SEP DAC39RFS10-SP, DAC39RFS10-SEP SBAS932A – MARCH 2024 – REVISED FEBRUARY 2026 www.ti.com 8 Submit Document Feedback Copyright © 2026 Texas Instruments Incorporated Product Folder Links: DAC39RF10-SP DAC39RF10-SEP DAC39RFS10-SP DAC39RFS10-SEP |
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