DAC39RF10 datasheet(99/232 Pages) TI2

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7.3.3 DEM and Dither

The device contains two optional features to improve non-linearity due to current segment and switch timing

mismatch: Dynamic element Mixing (DEM) and dither.

The DAC core consists of

1. Thermometer encoded current sources/switches representing the upper MSBs

2. Thermometer encoded current sources/switches representing the middle bits (called ULSBs)

3. Binary weighted current sources/switches representing the lower LSBs.

4. Additional current sources/switches for dithering

DEM randomizes which MSB and ULSB current sources/switches are used to generate the output, which

whitens the non-linearity due to mismatches between the current sources and switch timing. The DEM_DACA/B

and DEM_ADJ registers control the frequency and amplitude of the shift in current sources/segments.

Dither add or subtracts 8 different digital code values to the digital data which are then canceled by switching

additional current sources with the same amplitude. The digital data path is expanded so the full 16-bit range is

maintained. The DITH_DACA/B registers control the frequency of the dither.

Using DEM generally improves low order harmonics near fullscale. Dither generally improves higher order

harmonics near fullscale and all harmonics at lower digital amplitudes. Both DEM and dither increase the noise

floor (both amplitude and phase) of the output due to the whitening of the non-linearity and the additional

switching activity. This is reduced by DEM and dither settings with lower switching activity, that is. data

dependent or reduced activity DEM. However, data dependent or reduced activity DEM is less effective at

higher output frequencies. For data sheet specification testing in Electrical Characteristics - AC Specifications,

data dependent DEM (DEM_ADJ = 1) is used below 750MHz and normal activity DEM (DEM_ADJ = 0) above

750MHz, but different settings (including disabling DEM and/or dither) can be tested and the best chosen based

on the specific use case.

7.3.4 Offset Adjustment

The device allows an offset adjustment to the signal at the DAC output. The offset adjustment does NOT take

away from the full 16-bit digital range of the DAC data.

The offset is set by the DAC_OFS[0] or DAC_OFS[1] register values for DACA and DACB, respectively. If

dithering is enabled (see register DEM_DITH), the value is saturated to the range of ±128. If dithering is

disabled, the value is saturated to the range ±3968. This makes sure that the primary DAC range will never be

exceeded.

7.3.5 Clocking Subsystem

The device requires a clock running at a frequency equal to the DAC core sampling rate in NRZ, RTZ and RF

modes, or at half of the DAC core sampling rate in DES mode. The clocking subsystem is shown in Figure 7-12.

CLK+

CLKt

SYSREF+

SYSREFt

SYSREF Window

To DAC cores,

digital logic,

SerDes, ...

Figure 7-12. Device Clocking Subsystem

7.3.5.1 SYSREF Frequency Requirements

The SYSREF input period must be an integer multiple of all clocks in the part, including the LMFC/LEMC. The

following table depicts the requirements for the SYSREF period:

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DAC39RF10-SP, DAC39RF10-SEP

DAC39RFS10-SP, DAC39RFS10-SEP

SBAS932A – MARCH 2024 – REVISED FEBRUARY 2026

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DAC39RF10 Datasheet(PDF) 99 Page - Texas Instruments

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