DAC39RF10 datasheet(101/232 Pages) TI2

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SYSREF_PS_EN is enabled has a 1 in a position, the SYSREF_POS value is set to one. This provides worst

case values for SYSREF_POS to select the optimum SYSREF_SEL setting.

Table 7-4. Examples of SYSREF_POS Readings and SYSREF_SEL Selections

SYSREF_POS[19:0]

OPTIMAL SYSREF_SEL

SETTING

0x092[3:0]

(positions 19-16)

0x091[7:0](1)(positions 15-8)

0x090[7:0](1)

(positions 7-0)

b1000

b01100000

b00011001

8 or 9

b1000

b00000000

b00110001

b1000

b01100000

b00000001

6 or 7

b1000

b00000011

b00000001

4 or 14

b1100

b01100011

b00011001

(1)

Underlined 0 indicates the bits that are selected, as given in the last column of this table.

To use SYSREF Windowing:

1. Apply SYSREF and CLK

2. Set SYSREF_RECV_SLEEP = 0 and SYSREF_ZOOM = 1

3. If persistence is desired, set SYSREF_PS_EN = 1 and allow many SYSREF transitions for SYSREF_POS to

build.

4. Read SYSREF_POS and determine a proper setting for SYSREF_SEL, as shown above. If a proper

sampling point cannot be determined, set SYSREF_ZOOM = 0 and retry.

5. Once a proper value for SYSREF_SEL is applied, program SYSREF_PROC_EN = 1 and

SYSREF_ALIGN_EN = 1.

6. SYSREF is now being properly processed by the device and the user can proceed to use the JESD204C

interface (or other functionality) that relies on SYSREF.

7. SYSREF may need to be adjusted over large temperature or supply voltage swings, depending on the input

clock frequency. The SYSREF invalid window dependence on temperature (tINV(TEMP)) and VA11 supply

voltage (tINV(VA11)) is given in Section 6.8. To adjust SYSREF_SEL to track shifts in SYSREF relative to the

input clock, the following steps can be looped (that is, in background during operation of the JESD204C link):

a. If persistence is desired, clear and then set SYSREF_PS_EN, and allow many SYSREF transitions for

the SYSREF_POS data to build.

b. Read SYSREF_POS and determine a new value for SYSREF_SEL (but do not program it yet).

The procedure to incrementally adjust SYSREF_SEL should prefer values that are closer to the

previousSYSREF_SEL value rather than selecting the smallest valid SYSREF_SEL value. This helps

make sure that the original valid window is selected and tracked rather than selecting a different window

which would cause clock realignment to occur.

c. Program SYSREF_PROC_EN = 0. Write the new SYSREF_SEL value, and then set

SYSREF_PROC_EN = 1. The new SYSREF_SEL value is now used by the device.

d. Wait for some period of time, then return to step 7a above.

7.3.6 Digital Signal Processing Blocks

The digital signal processing blocks are shown in Figure 7-13. The device includes four digital up-converter

(DUC) blocks supporting four complex (IQ) input streams that can be combined at different RF frequencies. The

four DUCs can be flexibly assigned and summed together for either DAC output in the channel bonder. The final

signal processing block is a extra interpolate by 2 filter for use with DES2XL/H mode.

Table 7-5 and Table 7-6 list the available modes for single channel and dual channel outputs, respectively.

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DAC39RF10-SP, DAC39RF10-SEP

DAC39RFS10-SP, DAC39RFS10-SEP

SBAS932A – MARCH 2024 – REVISED FEBRUARY 2026

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