DAC39RF10 datasheet(42/232 Pages) TI2

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6.8 Timing Requirements

Typical values at TA = +25°C, minimum and maximum values over operating free-air temperature range, typical supply

voltages, fCLK = 10.24 GHz, IFS_SWITCH = 20.5 mA, single tone amplitude = 0 dBFS, Dither and DEM enabled, unless

otherwise noted.

MIN

NOM

MAX

UNIT

INPUT CLOCK (CLK+, CLK-)

fCLK

Input clock frequency

800

10400

MHz

SYSREF (SYSREF+, SYSREF-)

tSYSREF_LOW

SYSREF Low Timing

5*tCLK +

1 ns

tSYSREF_HIGH

SYSREF High Timing

5*tCLK +

1 ns

tINV(SYSREF)

Width of invalid SYSREF capture region of CLK± period, indicating setup or

hold time

violation, as measured by SYSREF_POS status register(1)

tINV(TEMP)

Drift of invalid SYSREF capture region over temperature, positive number

indicates a shift toward MSB of SYSREF_POS register

–0.05

ps/°C

tINV(VA11)

Drift of invalid SYSREF capture region over VDDSYS18 supply voltage,

positive number indicates a shift toward MSB of SYSREF_POS register

0.19

ps/mV

tSTEP(SP)

Delay of SYSREF_POS LSB

SYSREF_ZOOM = 0

SYSREF_ZOOM = 1

DC(SYSREF)

SYSREF duty cycle (asserted) when

using a periodic SYSREF signal

SYSREF duty cycle (asserted) when

using a periodic SYSREF signal

50%

55%

t(PH_SYS)

Minimum SYSREF± assertion duration after SYSREF± rising edge event

RESET

tRESET

Minimum RESET pulse width

100

TXENABLE

tTXENABLE_LOW

TXENABLE Low Time

102

clock

cycles

(1)

Use SYSREF_POS to select an optimal SYSREF_SEL value for the SYSREF capture, see the SYSREF Position Detector section for

more information on SYSREF windowing. The invalid region, specified by tINV(SYSREF), indicates the portion of the CLK± period(tCLK),

as measured by SYSREF_SEL, that may result in a setup and hold violation. Verify that the timing skew between SYSREF± and

CLK± over system operating conditions from the nominal conditions (that used to find optimal SYSREF_SEL) does not result in the

invalid region occurring at the selected SYSREF_SEL position in SYSREF_POS, otherwise a temperature dependent SYSREF_SEL

selection may be needed to track the skew between CLK± and SYSREF±.

DAC39RF10-SP, DAC39RF10-SEP

DAC39RFS10-SP, DAC39RFS10-SEP

SBAS932A – MARCH 2024 – REVISED FEBRUARY 2026

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Product Folder Links: DAC39RF10-SP DAC39RF10-SEP DAC39RFS10-SP DAC39RFS10-SEP

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