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5P35021 Datasheet(PDF) 1 Page - Renesas Technology Corp |
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5P35021 Datasheet(HTML) 1 Page - Renesas Technology Corp |
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1 / 48 page  1 ©2016-2026 Renesas Electronics Corporation June 2, 2026 Description The 5P35021 is a VersaClock programmable clock generator and is designed for low-power, consumer, and high-performance PCI Express applications. The 5P35021 device is a three PLL architecture design, and each PLL is individually programmable and allowing for up to six unique frequency outputs. The 5P35021 has built-in unique features such as Proactive Power Saving (PPS), Performance-Power Balancing (PPB), Overshot Reduction Technology (ORT) and Extreme Low Power DCO. An internal OTP memory allows the user to store the configuration in the device. After power up, the user can change the device register settings through the I2C interface when I2C mode is selected. The device has programmable VCO and PLL source selection to allow the user to do power-performance optimization based on the application requirements. It also supports three single-ended outputs and two pair of differential outputs that support LVCMOS, LVPECL, LVDS and LP-HCSL. A Low Power 32.768kHz clock is supported with only less than 2µA current consumption for system RTC reference clock. Typical Applications ▪ PCIe Gen1–3 clock generator ▪ Consumer application crystal replacements ▪ SmartDevice, Handheld ▪ Computing and consumer applications ▪ Automotive applications (infotainment, dashboard, camera/vision, computing, networking) Key Specifications ▪ PCIe clocks phase jitter: PCIe Gen3 ▪ Differential clocks < 1.5ps rms jitter integer range 12kHz–20MHz Features ▪ Configurable OE pin function as OE, PD#, PPS or DFC control function ▪ Configurable PLL bandwidth; minimizes jitter peaking ▪ PPS: Proactive Power Saving features save power during the end device power down mode ▪ PPB: Performance Power Balancing feature allows minimum power consumption based on required performance ▪ DFC: Dynamic Frequency Control feature allows user to dynamically switch between and up to 4 different frequencies smoothly ▪ Two PLLs support independent spread spectrum clocks to lower system EMI ▪ Store user configuration into OTP memory ▪ I2C interface ▪ Available in two temperature ranges: • Automotive (AEC-Q100 Grade 2): -40°C to +105°C • Industrial: -40°C to +85°C Output Features ▪ 2 DIFF outputs with configurable LP-HSCL, LVDS, LVPECL, LVCMOS output pairs. 1MHz–500MHz (160MHz with LVCMOS mode) ▪ 1 LVCMOS outputs: 1MHz–160MHz ▪ Maximum 5 LVCMOS outputs as 1× dedicated SE output and 2 DIFF outputs as 4 single ended outputs ▪ Low power 32.768kHz clock supported for SE1 output 5P35021 Datasheet VersaClock® Programmable Clock Generator |
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