ETA1188

www.etasolution.com

5

Powering Minds of the Smart

PIN DESCRIPTION

PIN #

PIN NAME

DESCRIPTION

1

SCL

I2C interface clock. Connect a 10-kΩ pull up resistor to VLDO or external 3.3V

rail.

2

BOOT

Bootstrap capacitor connection for the high-side FET gate driver. Connect a

10-nF ceramic capacitor (voltage rating ≥ 10 V) from BOOT pin to SW pin.

3, 13

VOUT

Output pins. Connect a 2x22uF to GND

4, 12

PMID

Midpoint of the Boost output and current limit switch. Connect a 22uF to GND

5, 7, 9, 11

SW

Switching Pin. Connect with an inductor between this pin and input.

6, 8, 10

PGND

Power Ground.

14

ISET

Boost maximum output current setting. Connect a resistor between this pin

and analog ground to set the current level.

15

VIN

Input pin. Connect to Battery or input supply. Bypass with a 22uF capacitor

from this pin to ground.

16

FB

Feedback pin for setting up the boost output voltage.

17

AGND

Analog Ground pin.

18

EN

Enable pin for the IC.

19

VLDO

LDO Regulator Output. Bypass with 1uF capacitor from this pin to ground.

20

SDA

I2C interface data. Connect a 10-kΩ pull up resistor to VLDO or external 3.3V

rail.

FUNCTIONAL BLOCK DIAGRAM

PWM

CONTROL&

DRIVER

CHARGE

PUMP

LDO

( From PMID)

AGND

BANDGAP

EN

THERMAL

SHUTDOWN

VIN UVLO

HICCUP&

SOFTSTART

Gmi

Gmv

VDD

1V

1.2V

COMP

Σ

OSC

VOUT

I2C

SDA

SCL

VOUT

IOREG

[2:0]

VOREG

[8:0]

ISET

PMID

BOOT

SW

PGND

VIN

VLDO

FB

ETA1188

Figure 2: ETA1188 Function Block Diagram