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FN6406 Datasheet(PDF) 9 Page - Renesas Technology Corp

Part # FN6406
Description  Triple Differential Receiver/Equalizer
PDF  13 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

FN6406 Datasheet(HTML) 9 Page - Renesas Technology Corp

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FN6406 Rev 1.00
Page 9 of 13
Sep 28, 2018
ISL59910, ISL59913
Applications Information
Logic Control
The ISL59913 has two logical input pins, Chip Enable
(ENABLE) and Switch Gain (X2). The logic circuits all have a
nominal threshold of 1.1V above the potential of the logic
reference pin (VREF). In most applications it is expected that
this chip runs from a +5V, 0V, -5V supply system with logic
being run between 0V and +5V. In this case, tie the logic
reference voltage to the 0V supply. If the logic is referenced to
the -5V rail, connect the logic reference to -5V. The logic
reference pin sources about 60µA and this rises to about
200µA if all inputs are true (positive).
The logic inputs all source up to 10µA when they are held at
the logic reference level. When taken positive, the inputs sink a
current dependent on the high level, up to 50µA for a high level
5V above the reference level.
If the logic inputs are not used, tie them to the appropriate
voltage to define their state.
Control Reference and Signal Reference
Analog control voltages are required to set the equalizer and
contrast levels. These signals are voltages in the range 0V to
1V, which are referenced to the control reference pin. It is
expected that the control reference pin is tied to 0V and the
control voltage varies from 0V to 1V. It is, however, acceptable
to connect the control reference to any potential between -5V
and 0V to which the control voltages are referenced.
The control voltage pins themselves are high impedance. The
control reference pin sources between 0µA and 200µA
depending on the control voltages being applied.
The control reference and logic reference effectively remove the
necessity for the 0V rail and operation from ±5V (or 0V and 10V)
only is possible. However, we still need a further reference to
define the 0V level of the single-ended output signal. The
reference for the output signal is provided by the 0V pin. The
output stage cannot pull fully up or down to either supply so it is
important that the reference is positioned to allow full output
swing. Tie the 0V reference to a quiet reference as any noise on
this pin is transferred directly to the output. The 0V pin is a high
impedance pin and draws DC bias currents of a few µA and
similar levels of AC current.
Equalizing
When transmitting a signal across a twisted pair cable, the high
frequency (above 1MHz) information is attenuated more
significantly than the information at low frequencies. The
attenuation is predominantly due to resistive skin effect losses
and has a loss curve which depends on the resistivity of the
conductor, surface condition of the wire, and the wire diameter.
For the range of high performance twisted pair cables based
on 24awg copper wire (CAT-5 etc), these parameters vary only
a little between cable types and in general cables exhibit the
same frequency dependence of loss. (The lower loss cables
can be compared with somewhat longer lengths of similar
cables.) This enables a single equalizing law equation to be
built into the ISL59913.
With a control voltage applied between pins VCTRL and VREF,
the frequency dependence of the equalization is shown in
Figure 8 on page 6. The equalization matches the cable loss
up to about 100MHz. Above this, system gain is rolled off
rapidly to reduce noise bandwidth. The roll-off occurs more
rapidly for higher control voltages, thus the system (cable +
equalizer) bandwidth reduces as the cable length increases.
This is desirable, as noise increases as the equalization
increases.
Typical Performance Curves (Continued)
FIGURE 23. PACKAGE POWER DISSIPATION vs AMBIENT
TEMPERATURE
FIGURE 24. PACKAGE POWER DISSIPATION vs AMBIENT
TEMPERATURE
JEDEC JESD51-7 HIGH EFFECTIVE THERMAL
CONDUCTIVITY TEST BOARD - QFN EXPOSED
DIEPAD SOLDERED TO PCB PER JESD51-5
JA =
37°C
/W
QF
N28
3.378W
0
50
85
150
4.5
3.5
2.5
1.5
0.5
0
AMBIENT TEMPERATURE (°C)
25
75
100
125
4
2
1
3
JEDEC JESD51-3 LOW EFFECTIVE THERMAL
CONDUCTIVITY TEST BOARD
893mW
JA =
140
°C/W
QF
N28
0
50
85
150
1.2
0.8
0.6
0.4
0.2
0
AMBIENT TEMPERATURE (°C)
25
75
100
125
1



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