Electronic Components Datasheet Search
  English  ▼

X  

Preview PDF HTML

LAN9312 Datasheet(PDF) 110 Page - SMSC Corporation

Part # LAN9312
Description  High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface
PDF  458 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Manufacturer  SMSC [SMSC Corporation]
Direct Link  http://www.smsc.com
Logo SMSC - SMSC Corporation

LAN9312 Datasheet(HTML) 110 Page - SMSC Corporation

Back Button LAN9312 Datasheet HTML 106Page - SMSC Corporation LAN9312 Datasheet HTML 107Page - SMSC Corporation LAN9312 Datasheet HTML 108Page - SMSC Corporation LAN9312 Datasheet HTML 109Page - SMSC Corporation LAN9312 Datasheet HTML 110Page - SMSC Corporation LAN9312 Datasheet HTML 111Page - SMSC Corporation LAN9312 Datasheet HTML 112Page - SMSC Corporation LAN9312 Datasheet HTML 113Page - SMSC Corporation LAN9312 Datasheet HTML 114Page - SMSC Corporation Next Button
Zoom Inzoom in Zoom Outzoom out
 110 / 458 page
background image
High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface
Datasheet
Revision 1.2 (04-08-08)
110
SMSC LAN9312
DATASHEET
8.4.8
PIO Writes
PIO writes are used for all LAN9312 write cycles. PIO writes can be performed using Chip Select (nCS)
or Write Enable (nWR). A PIO write cycle begins when both nCS and nWR are asserted. The cycle
ends when either or both nCS and nWR are de-asserted. Either or both of these control signals must
de-assert between cycles for the period specified in Table 15.12, “PIO Write Cycle Timing Values,” on
page 451. They may be asserted and de-asserted in any order. Either or both of these control signals
must be de-asserted between cycles for the period specified. The PIO write cycle is illustrated in the
functional timing diagram in Figure 8.7.
The END_SEL signal has the same timing characteristics as the address lines.
Please refer to Section 15.5.8, "PIO Write Cycle Timing," on page 451 for the AC timing specifications
for PIO write operations.
Figure 8.7 Functional Timing for PIO Write Operation
VALID
VALID
D[31:0] (INPUT)
nCS, nWR
A[x:2]
VALID
END_SEL



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100  ...More


Datasheet Download

Go To PDF Page


Link URL



Does ALLDATASHEET help your business so far?  [ DONATE ] 

About Alldatasheet   |   Advertisement   |   Contact us   |   Privacy Policy   |   Link to Datasheet    |   Link Exchange   |   Manufacturer List
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com