LAN9312 datasheet(107/458 Pages) SMSC

107 / 458 page

High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface

Datasheet

SMSC LAN9312

107

Revision 1.2 (04-08-08)

DATASHEET

8.4.5

PIO Burst Reads

In this mode, performance is improved by allowing up to 8 DWORD read cycles back-to-back. PIO

burst reads can be performed using Chip Select (nCS) or Read Enable (nRD). A PIO Burst Read

begins when both nCS and nRD are asserted. Either or both of these control signals must de-assert

between bursts for the period specified in Table 15.9, “PIO Burst Read Cycle Timing Values,” on

page 448. The burst cycle ends when either or both nCS and nRD are de-asserted. They may be

asserted and de-asserted in any order. Read data is valid as indicated in the functional timing diagram

in Figure 8.4.

Note:

Fresh data is supplied each time A[2] toggles.

The endian select signal (END_SEL) has the same timing characteristics as the upper address lines.

Please refer to Section 15.5.5, "PIO Burst Read Cycle Timing," on page 448 for the AC timing

specifications for PIO burst read operations.

Note:

PIO burst reads are only supported for the RX Data FIFO. Burst reads from other registers are

not supported.

Figure 8.4 Functional Timing for PIO Burst Read Operation

END_SEL

A[x:5]

A[4:2]

nCS, nRD

D[31:0] (OUTPUT)

VALID

LAN9312 Datasheet(PDF) 107 Page - SMSC Corporation