LAN9312 datasheet(111/458 Pages) SMSC

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High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface

Datasheet

SMSC LAN9312

111

Revision 1.2 (04-08-08)

DATASHEET

8.4.9

TX Data FIFO Direct PIO Writes

In this mode only A[2] is decoded, and any write to the LAN9312 will write the TX Data FIFO. This

mode is enabled when FIFO_SEL is driven high during a write access. This is normally accomplished

by connecting the FIFO_SEL signal to a high-order address line. This mode is useful when the host

processor must increment its address when accessing the LAN9312.

Timing is identical to a PIO write, and the FIFO_SEL and END_SEL signals have the same timing

characteristics as the address lines. A TX Data FIFO direct PIO write cycle begins when both nCS and

nWR are asserted. Either or both of these control signals must de-assert between cycles for the period

specified in Table 15.13, “TX Data FIFO Direct PIO Write Cycle Timing Values,” on page 452. The cycle

ends when either or both nCS and nWR are de-asserted. They may be asserted and de-asserted in

any order. The TX Data FIFO direct PIO write cycle is illustrated in the functional timing diagram in

Figure 8.8.

Note:

A[9:3] are ignored during TX Data FIFO direct PIO writes.

Please refer to Section 15.5.9, "TX Data FIFO Direct PIO Write Cycle Timing," on page 452 for the AC

timing specifications for TX Data FIFO direct PIO write operations.

8.5

HBI Interrupts

The HBI allows access to all interrupt configuration and status registers within the LAN9312. The

LAN9312 implements a multi-tier interrupt hierarchy with the Interrupt Configuration Register

(IRQ_CFG), Interrupt Status Register (INT_STS), and Interrupt Enable Register (INT_EN) at the top

level. These registers allow for the configuration of which interrupts trigger the IRQ, as well as the IRQ

deassertion and polarity properties. Interrupts may be generated from the 1588 Timestamping, Switch

Fabric, Port 1 PHY, Port 2 PHY, Host MAC, EEPROM Loader, General Purpose Timer, General

Purpose I/O, and Power Management blocks.

For more information of the LAN9312 interrupts, refer to Chapter 5, System Interrupts.

Figure 8.8 Functional Timing for TX Data FIFO Direct PIO Write Operation

VALID

D[31:0] (INPUT)

nCS, nWR

A[x:3]

VALID

END_SEL

VALID

A[2]

FIFO_SEL

(WRITE DATA TO TX DATA FIFO)

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