LAN9312 datasheet(121/458 Pages) SMSC

121 / 458 page

High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface

Datasheet

SMSC LAN9312

121

Revision 1.2 (04-08-08)

DATASHEET

RX data. The MIL FIFOs are essentially the working buffers of the Host MAC logic. In the case of

reception, the data must be moved into the RX FIFOs before the host can access the data.

As space in the TX MIL FIFO frees, data is moved into it from the TX Data FIFO. Depending on the

size of the frames to be transmitted, the Host MAC can hold up to two Ethernet frames. This is in

addition to any TX data that may be queued in the TX Data FIFO.

Conversely, as data is received, it is moved from the Host MAC to the RX MIL FIFO, and then into

the RX Data FIFO. When the RX Data FIFO fills up, data will continue to collect in the RX MIL FIFO.

If the RX MIL FIFO fills up and overruns, subsequent RX frames will be lost until room is made in the

RX Data FIFO. For each frame of data that is lost, the Host MAC RX Dropped Frames Counter

RX and TX MIL FIFO levels are not visible to the host processor and operate independent of the

TX/RX FIFOs. FIFO levels set for the TX/RX Data and Status FIFOs do not take into consideration the

MIL FIFOs.

9.7.3

FIFO Memory Allocation Configuration

TX and RX FIFO space is configurable through the Hardware Configuration Register (HW_CFG). The

user must select the FIFO allocation by setting the TX FIFO Size (TX_FIF_SZ) field in the Hardware

Configuration Register (HW_CFG). The TX_FIF_SZ field selects the total allocation for the TX data

path, including the TX Status FIFO size. The TX Status FIFO size is fixed at 512 Bytes (128 TX Status

DWORDs). The TX Status FIFO length is subtracted from the total TX FIFO size with the remainder

being the TX Data FIFO Size. The minimum size of the TX FIFOs is 2KB (TX Data and TX Status

FIFOs combined). Note that TX Data FIFO space includes both commands and payload data.

RX FIFO Size is the remainder of the unallocated FIFO space (16384 bytes – TX FIFO Size). The RX

Status FIFO size is always equal to 1/16 of the RX FIFO size. The RX Status FIFO length is subtracted

from the total RX FIFO size with the remainder being the RX Data FIFO Size.

For example, if TX_FIF_SZ = 6 then:

Total TX FIFO Size = 6144 Bytes (6KB)

TX Status FIFO Size = 512 Bytes (Fixed)

TX Data FIFO Size = 6144 – 512 = 5632 Bytes

RX FIFO Size = 16384 – 6144 = 10240 Bytes (10KB)

RX Status FIFO Size = 10240 / 16 = 640 Bytes (160 RX Status DWORDs)

RX Data FIFO Size = 10240 – 640 = 9600 Bytes

Table 9.8 contains an overview of the configurable TX/RX FIFO sizes and defaults. Table 9.9 shows

every valid setting for the TX_FIF_SZ field and the resulting FIFO sizes. Note that settings not shown

in this table are reserved and should not be used.

Note:

The RX Data FIFO is considered full 4 DWORDs before the length that is specified in the

HW_CFG register.

Table 9.8 TX/RX FIFO Configurable Sizes

FIFO

SIZE RANGE

DEFAULT

TX Status

512

RX Status

128-892

704

TX Data

1536-13824

4608

RX Data

1920-13440

10560

LAN9312 Datasheet(PDF) 121 Page - SMSC Corporation

LAN9312 Datasheet(HTML) 121 Page - SMSC Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL